Dsp Peripheral Mapping - Texas Instruments OMAP5910 Technical Reference Manual

Table 3–2. DSP Peripheral Mapping
Start Byte Address (hex)
x000000
x001000
x001800
x002800
x005000
x005800
x006000
x006800
x008000
x009000
x0010000
x0010800
x0011800
x0012000
x0012800
x0017000
x019800
x01C800
x001E000
x001F000
x001F800
† All other I/O memory addresses are reserved.
‡ Internal wait states for accessing peripherals are set by strobe1 and strobe2 fields in TIPB CM register (see Section 3.5.1,
Control Mode Register).
†
Name
TIPB bridge
EMIF
DMA
I-cache
TIMER 1
TIMER 2
TIMER 3
WD_TIMER
CLKM 2
Level 2 interrupt handler
UART1
UART2
McBSP1
MCSI2
MCSI1
McBSP3
UART3
UART1, 2, 3 sharing switch
GPIO
Mailbox
DSP MPUI register
Word Address Strobe
00000 Strobe 1
00800 Fixed strobe period
00C00 Fixed strobe period
01400 Fixed strobe period
02800 Fixed strobe period
02C00 Fixed strobe period
03000 Fixed strobe period
03400 Fixed strobe period
04000 Strobe 1
04800 Fixed strobe period
08000 Strobe2
08400 Strobe2
08c00 Strobe2
09000 Strobe2
09400 Strobe2
0B800 Strobe2
0CC00 Strobe2
0E400 Strobe2
0F000 Strobe2
0F800 Strobe2
0FC00 Strobe2
DSP Subsystem
DSP Memory
‡
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