Prescale Sampling Clock Divider Value - Texas Instruments OMAP5910 Technical Reference Manual

7.8.2.2 Data Format
2
7.8.2.3 I C Reset
7.8.2.4 Prescaler (ICLK)
Figure 7–30. Prescale Sampling Clock Divider Value
0x0:
0x1:
0xFF:
Values after reset are low (All 8 bits).
Noise Filter
2
7.8.2.5 I C Interrupts
2
The I C controller operates in 16-bit word data format (byte write access
supported for the last access), and it supports endianism.
The I2C_EN bit in the I
2
I C module. When the system bus reset is removed (RESET_ = 1),
I2C_EN = 0 keeps the I
2
The I C module is operated with an internal ~12-MHz clock (ICLK). This clock
is generated via the I
register; I2C_PSC is used for dividing down the system peripheral clock
(MPUXOR_CK) to obtain a ~12-MHz clock for the I
Figure 7–30).
MPUXOR_CK
Divide by 1
Divide by 2
↓ ↓
Divide by 256
The noise filter suppresses any noise that is 50 ns or less. It is designed to
suppress noise with one ICLK assuming the lower and upper limits of ICLK are
8 MHz and 16 MHz respectively.
2
The I C module generates five types of interrupt: arbitration-lost, no-acknowl-
edge, registers-ready-for-access, receive, and transmit. These five interrupts
are accompanied with five interrupt masks and flags defined in the I2C_IE and
I2C_STAT registers respectively.
An arbitration-lost interrupt (AL) is generated when the I
procedure is lost.
2
C configuration register (I2C_CON) can also reset the
2
C module in reset state.
2
C prescaler block. The prescaler consists of an 8-bit
1
(PSC+1)
MPU Public Peripherals
Inter-Integrated Circuit Controller
2
C module (see
ICLK
2
C arbitration
7-65