Clock Control - Texas Instruments OMAP5910 Reference Manual

6.2.9

Clock Control

6.2.10 Initialization
6.2.11 Interrupt Support
6.2.11.1 Interrupt Events and Requests
6.2.11.2 Interrupt Multiplexing
SPRU890A
The DSP MMU module is clocked by the DSPMMU_CK included in the DSP
clock domain. The DSP domain clock can be divided by 1, 2, 4, or 8 to generate
the MMU clock by using the DSPMMUDIV bits of the ARM_CKCTL register.
By default, the DSPMMUDIV bits are set to divide-by-one mode.
DSPMMU_CK can be shut off by setting the GL_PDE bit of the
DSPMMU_IDLE_CTRL register (section 6.5.17).
Note:
The DSP MMU clock must follow these rules:
The DSP MMU clock frequency must be greater than or equal to the
-
traffic controller clock frequency.
The DSP MMU clock frequency must be 1 or 1/2 times the DSP
-
subsystem clock frequency.
The DSP MMU clock must be configured as described in section 6.2.9 before
programming the DSP MMU.
Preferably, the DSP MMU should be configured before the DSP core is taken
out of reset. Note that the LD_TLB_REG, TTB_H_REG, TTB_L_REG, and the
LOCK_REG registers cannot be written to once the table walking logic has
been enabled (TWL_EN = 1 in CNTL_REG).
The DSP MMU generates a single interrupt to the MPU core in response to a
translation error. The ISR then determines the cause of the interrupt by reading
the fault status register (FAULT_ST_REG). The ISR may take one of two
actions to clear the interrupt from the MMU:
The ISR may clear the error condition as described in section 6.2.7.
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The ISR may reset the DSP subsystem through the DSP_EN bit of the
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MPU-Reset-Control-1 Register (ARM_RSTCT1) and reset the DSP MMU
through the MMU_RESET bit of the control register (CNTL_REG).
The DSP MMU interrupt is managed by the MPU level 2 interrupt handler.
Before the MPU core can see the DSP MMU interrupt, DSP_MMU_IRQ
(IRQ_28) must be enabled and configured as a level-sensitive interrupt. More
information on the MPU level 2 interrupt handler can be found in the
OMAP5912 Multimedia Processor Interrupts Reference Guide (SPRU757).
DSP Memory Management Unit
DSP Subsystem 95