Write Cycle - Texas Instruments OMAP5910 Reference Manual

Dual-core processor microwire interface
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MicroWire Interface
1.3.2

Write Cycle

20
MicroWire Interface
8) Set the following fields of the control and status register (CSR):
NB_BITS_RD: 16 (decimal)
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NB_BITS_WR: 0 (decimal)
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INDEX: 00
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CS_CMD: 1
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START: 1
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Go to 5.
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9) Set the following fields of the control and status register (CSR):
INDEX: 00
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CS_CMD: 0
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START: 0
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1) Set the following fields of the control and status register (CSR):
NB_BITS_RD: 0
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NB_BITS_WR: 0
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INDEX: 00
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CS_CMD: 1
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START: 0
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2) Load the transmit data register (TDR) with:
1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 x x x x x x: Don't care
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A7 ... A0: Address of the selected memory register
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3) Wait for the CSRB bit of the control and status register (CSR) to be reset.
4) Set the following fields of the control and status register (CSR):
NB_BITS_RD: 0
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NB_BITS_WR: 11 (decimal)
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INDEX: 00
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CS_CMD: 1
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START: 1
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5) Wait for the CSRB bit of the control and status register (CSR) to be reset.
6) Load the transmit data register (TDR) with:
D15 D14 ... D0
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D15 ... D0: Data
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SPRU686

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