Level-Sensitive Clear Low Register (Rst_Lvl_Lo) - Texas Instruments OMAP5910 Technical Reference Manual

DSP Interrupt Interface
8.5.4.1 Level-Sensitive Clear Commands (Write Only)
Table 8–33. Level-Sensitive Clear Low Register (RST_LVL_LO)
Bit Name
15–0 Reset_CHx
Table 8–34. Level-Sensitive Clear High Register (RST_LVL_HI)
Bit Name
7 Reset_NHOSTINT
6 Reset_NMI
8-30
A write transaction issues a clear to those interrupt channels whose assigned
bit in the 16-bit word being written is 1. Commands to clear interrupt channels
are necessary for those channels assigned as level-sensitive interrupt chan-
nels. Figure 8–6 illustrates the alignment of the channel clear assignments
within the 16-bit word written to the XIO interrupt processor and gives the
permissible range of addresses over which the write can take place.
A write to the level-sensitive clear low register (RST_LVL_LO), whose offset
address is 02, clears interrupts corresponding to nXIRQ[15:0].
Value Description
Reset CHx if a 1 is written into RST_LVL_LO[x] and CHx
is configured as level-sensitive interrupt, where CHx
corresponds to interrupt channels nXIRQ[15:0]
0 Do not reset CHx.
1 Reset interrupt channel CHx if level is configured as level
sensitive.
A write to the level-sensitive clear high register (RST_LVL_HI), whose offset
address is 03, clears interrupts from interrupt channels [20:16], NMI, and
HOSTINT.
Value Description
Reset NHOSTINT channel if a 1 is written into this
bit and NHOSTINT is configured as level-sensitive
interrupt.
0 Do not reset NHOSTINT.
1 Reset NHOSTINT interrupt channel, if configured
as level-sensitive interrupt.
Reset NMI channel if a 1 is written into this bit and
NMI is configured as level-sensitive interrupt.
0 Do not reset CHx.
1 Reset NMI interrupt channel if configured as
level-sensitive interrupt.
Reset
Type
Value
0 0
Reset
Type
Value