Burst Read Operation; Asynchronous Page Mode 8X16-Bit Read With Page Crossing On 16-Bit Width - Texas Instruments OMAP5910 Reference Manual

Figure 5.

Asynchronous Page Mode 8x16-Bit Read With Page Crossing on 16-Bit Width

Device (4 Words per Page)
TC Clock
(internal)
EMIFS Ref
(internal)
FLASH.CLK
FLASH.CS_[X]
FLASH.ADV
FLASH.A(24:1)
FLASH.D(15:0)
FLASH.OE
FLASH.RDY
FLASH.BE(1:0)
3.2.7

Burst Read Operation

SPRU673
N cycles
P cycles
Add0 Add1
D0 D1
The synchronous read mode is selected for each device by setting the
RDMODE configuration bit field to 100b.
In this mode of operation, FLASH.CLK is driven on the OMAP5910 device pin.
Both AMD burst flash and Intel burst flash have three modes of operation:
Asynchronous single read mode (default)
-
Synchronous single read or burst read mode
-
Asynchronous write
-
Asynchronous single read mode and asynchronous write modes are
compatible with operation described in Section 3.2.5, Asynchronous Read
Operation, and Section 3.2.8, Asynchronous Write With WE Operation.
Figure 6 shows the timing view of synchronous burst read mode operation.
On the AMD device, LBA is directly connected to the FLASH.ADV OMAP5910
pin.
The address is latched on the rising edge of FLASH.ADV with a specified hold
time of 3 ns. This is easily met by maintaining the address during two cycles.
Data output of the device is stable on the rising edge of FLASH.CLK (specified
with a setup and hold time referenced to this edge).
Low
N cycles
Add2 Add3 Addr4
D2 D3
High
Memory Interface Traffic Controller
Memory Interfaces
P cycles
Add5 Add6 Add7
D4 D5 D6 D7
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