Peripheral Register Addresses - Texas Instruments OMAP5910 Technical Reference Manual

DSP Memory
3.3.5

Peripheral Register Addresses

3-14
The DSP CPU and the DMA controller can access several classes of
peripheral devices:
-
DSP private peripherals (see Chapter 8)
J
Three general-purpose timers
J
A watchdog timer
J
An interrupt handler
-
MPU/DSP shared peripherals (see Chapter 10)
J
Communications mailbox
J
GPIO control
J
General-purpose UART
-
DSP public peripherals (see Chapter 9)
J
Two multichannel buffered serial ports (McBSPs) for synchronous
serial communications
J
Two multichannel serial interfaces (MCSIs)
Configuration and data registers for all peripherals reside in the DSP subsys-
tem I/O space, which consists of 64K-word addresses, with each peripheral
mapping into a 1K-word section of I/O memory. To read or write these regis-
ters, you must access the DSP I/O space either through C language constructs
or by using the assembly language peripheral port register access qualifier.
See TMS320C55x DSP Mnemonic Instruction Set Reference Guide
(SPRU374D) for more details.
Table 3–2 shows the DSP peripheral mapping.