Digital Signal Processor Subsystem Overview; Architecture Overview; Features - Texas Instruments OMAP5910 Reference Manual

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Digital Signal Processor Subsystem Overview

1.1

Architecture Overview

1.2

Features

SPRU890A
The Digital Signal Processor (DSP) Subsystem is a collection of modules
which include the TMS320C55x CPU processor along with its hardware
accelerators, tightly coupled memory, instruction cache, and dedicated DMA,
the interfaces it uses to communicate with rest of the OMAP device, as well
as a number of peripherals.
The TMS320C55x core processor (also referred to as the DSP core) and the
peripherals included in the DSP subsystem communicate with:
The MPU core via the microprocessor unit interface (MPUI)
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Various standard memories via the external memory interface (EMIF)
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Various system peripherals via two TI peripheral bus (TIPB) bridges
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Figure 1 and Figure 2 in section 1.4 show block diagrams for the OMAP5910
and OMAP5912 DSP subsystems.
The DSP subsystem is composed of several portions: the DSP module, the
peripherals that surround that module, and several interfaces used to
communicate with the rest of the OMAP modules. Each portion has the
following components:
DSP module:
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TMS320C55x (C55x) DSP core
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Tightly coupled
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transform/inverse discrete cosine transform (DCT/IDCT), motion
estimation, and half-pixel interpolation
Tightly coupled memories and their interfaces: dual-access RAM
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(DARAM), single-access RAM (SARAM), programmable dynamic
ROM, and an instruction cache (I-Cache)
Six-channel DMA controller that can copy memory contents from one
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address to another without DSP core intervention
DSP Subsystem
hardware accelerators:
DSP Subsystem
discrete cosine
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