Emif Requests Associated With Dual And Long Data Accesses; Write Posting: Buffering Write To Dsp External Memory - Texas Instruments OMAP5910 Reference Manual

Table 15. EMIF Requests Associated with Dual and Long Data Accesses
DSP Core Data
Buses Used
Access Type
Dual data read CB and DB
(carrying two 16-bit values)
Dual data write EB and FB
(carrying two 16-bit values)
Long data read CB and DB
(carrying one 32-bit value)
Long data write EB and FB
(carrying one 32-bit value)
5.2.5

Write Posting: Buffering Write to DSP External Memory

SPRU890A
Typically, when a DSP core write request arrives at the EMIF, the EMIF does
not send acknowledgment to the DSP core until the EMIF has driven the data
on the external bus. As a result, the DSP core does not begin the next
operation until the data is actually sent to the DSP external memory.
If write posting is enabled, the EMIF acknowledges the DSP core as soon as
the EMIF receives the address and data. The address and data are stored in
dedicated write posting registers in the EMIF. When a time slot becomes
available, the EMIF runs the posted write operation. If the next DSP core
access is not for the EMIF and is for internal memory, that access is able to run
concurrently with the posted write operation.
The EMIF supports two levels of write posting. That is, the write posting
registers can hold data and addresses for up to two DSP core accesses at a
time. The EMIF allocates the write posting registers on a first requested, first
served basis. However, if the E bus and the F bus make requests
simultaneously, the E bus is given priority.
To enable write posting for all accesses to DSP external memory, set the WPE
bit in the EMIF global control register. It might be useful to disable write posting
(WPE = 0) during debugging.
There are no write posting registers for requests from the DMA controller.
However, the EMIF sends acknowledgement to the DSP DMA controller prior
to the actual write to DSP external memory. This early acknowledgement
allows the DMA controller to transfer the next address early, avoiding dead
cycles during burst transfers or between back-to-back single transfers.
DSP External Memory Interface
DSP Core Address
Bus(es) Used
Request(s) Sent To EMIF
CAB and DAB C-bus request to read 16 bits
D-bus request to read 16 bits
EAB and FAB E-bus request to write 16 bits
F-bus request to write 16 bits
DAB D-bus request to read 32 bits
EAB E-bus request to write 32 bits
DSP Subsystem 61