Dsp Memory - Texas Instruments OMAP5910 Technical Reference Manual

3.3 DSP Memory

The DSP subsystem contains four types of tightly coupled memory to enable
maximum efficiency of the DSP CPU.
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Dual-access RAM (DARAM)
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Single-access RAM (SARAM)
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Programmable dynamic ROM (PDROM)
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Configurable instruction cache structure
The CPU uses six sets of buses to simultaneously fetch up to 32 bits of pro-
gram and read up to 48 bits of data operands from memory (or write up to
32 bits to memory). To achieve maximum performance from the architecture,
the programmer must pay close attention to placement of code and data struc-
tures within the on-chip memory resources. For more details, see
TMS320C55x DSP Programmers Guide (SPRU376) Chapters 3 and 4.
Loosely coupled memory devices can be accessed via the traffic controller
module. This flexible memory interface permits DSP access to another block
of SRAM (shared with the MPU) as well as external memory devices such as
flash memory and SDRAM.
Figure 3–5 shows DSP memory connections.
DSP Memory
DSP Subsystem 3-9