Watchdog Timer Characteristics; Programming The Watchdog Timer In Watchdog Mode - Texas Instruments OMAP5910 Technical Reference Manual

Watchdog Timer
Table 6–10. Watchdog Timer Characteristics
Input clock, t
clk
CLKIN Clock Period
12 MHz 1167 ns
12 MHz 1167 ns
† The 12-MHz clock is divided by 14.
6.3.2

Programming the Watchdog Timer in Watchdog Mode

6-10
t = t X (LOAD_TIM + 1) x 2
int clk
Table 6–10 shows the characteristics of the watchdog timer for different
LOAD_TIM values.
,
†
LOAD_TIM
0001
FFFF (max interrupt period)
If LOAD_TIM = 0 and AR (auto-reload mode) = 1, the timer is always 0 and can
never decrement. Here the timer interrupt is asserted and stays asserted all
the time. Since the timer interrupts are edge-senditive, only one interrupt is
recognized because there is one initial edge, and then the interrupt is asserted
constantly.
On power up, the watchdog timer defaults to watchdog mode and the value
loaded into the LOAD_TIM register is set to the maximum value (0xFFFF).
This gives the user a time of 16,777,216 * t
timer mode or write a new value (different from 0xFFFF) into the LOAD_TIM
register.
The user program or the OS must write periodically to the count register,
LOAD_TIM, before the counter underflows. The new loaded value must be
different from the previous value because the write is taken into account only
if the newly loaded value is different from the previous value. Due to internal
sequencing, the user must wait three timer clock periods before writing a new
value into the LOAD_TIM register. If CLKIN is 12 MHz, the duration of three
timer clock periods is approximately 3.5 µs.
By writing a predefined sequence (0xF5 followed by 0xA0) to the TIM-
ER_MODE register (see Table 6–15), the timer can be configured as a gener-
al-purpose timer. A sequence decode is initialized when 0xF5 is written to the
TIMER_MODE register. Once in this state, if the next write is different from
0xA0, the state machine causes a reset as if the watchdog timer has under-
flowed. You cannot disable the watchdog timer by simply clearing the watch-
dog bit of the TIMER_MODE register.
(PTV+1)
t , Timer Interrupt Period,
int
for PTV = 7
597.34 µs
19.57 s
(19.57 seconds) to change the
clk