Functional Multiplexing Control 7 Register (Func_Mux_Ctrl_7) - Texas Instruments OMAP5910 Technical Reference Manual

Table 6–35. Functional Multiplexing Control 7 Register (FUNC_MUX_CTRL_7)
Bits Name
31–21 RESERVED
20–18 CONF_ARMIO_2_R
17–15 CONF_ARMIO_4_R
14–12 CONF_ARMIO_5_R
11–9 CONF_GPIO_0_R
8–6 CONF_GPIO_1_R
5–3 CONF_GPIO_2_R
2–0 CONF_GPIO_3_R
Description
Reserved for future expansion. These bits must always
be written as 0.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to MPUIO2 at reset
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to MPUIO4 at reset
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to MPUIO5 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO0 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO1 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO2 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO3 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
OMAP5910 Configuration Registers
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MPU Private Peripherals
Reset
Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
6-37