Dsp Subsystem And Modules - Texas Instruments OMAP5910 Technical Reference Manual

Figure 3–2. DSP Subsystem and Modules
Endianism
conversion
EMIF
I-Cache
DSP
MMU
DARAM
SARAM
ROM,
SRAM,
PDROM
Traffic
Flash,
controller
SBFlash
SDRAM
On-chip
SARAM
DSP subsystem and interfaces
Internal
memory
buses
Memory
I/F
Shared
TIPB
bridge
Configuration
DMA
(EMIF)
(DARAM)
(SARAM)
(MPUI)
(TIPB)
MPUI port
Endianism conversion
MPU subsystem
MPUI
System
DMA
DSP private
peripherals
Timer
DSPTM_CK
DSP
(1 INT)
HWA
WD Timer
TMS320C55x
DSPWD_CK
DSP core
(1 INT)
Interrupt
handler
Private
DSP_INTH_CK
TIPB
bridge
Interrupt I/F
DSP_INTH_CK
DSP private peripheral bus
DSP public peripheral bus
Pseudo-
dynamic
MPU public
sharing
peripheral
bus
MPU public
TIPB bridge
MPU
Architecture Overview
MPU/DSP
shared
peripherals
Mailbox
GPIO I/F
1 INT to MPU
and/or DSP
MPU_GPIO_CK
UART1,2,3
Static UART
sharing switch
16
16
DSP public
peripherals
McBSP1 (Audio PCM)
I2S via McBSP
DSPXOR_CK
2 INT, 2DMA
McBSP3 (optical)
(McBSP)
DSPXOR_CK
2 INT, 2DMA
MCSI2
(MCSI)
DSPXOR_CK
2 INT
MCSI1(bluetooth voice)
(MCSI)
DSPXOR_CK
2 INT
DSP Subsystem 3-3