Sdram Autorefresh Initialization; Sdram Self-Refresh Protection - Texas Instruments OMAP5910 Reference Manual

3.3.4

SDRAM Autorefresh Initialization

3.3.5

SDRAM Self-Refresh Protection

SPRU673
To increase SDRAM bus availability, it is preferable to subdivide the SDRAM
into smaller sections and then evenly distribute the refresh of each of these
subsections instead of performing a single autorefresh for the entire SDRAM.
The OMAP5910 device can support subdividing the autorefresh of the
SDRAM into bursts of 1, 4, or 8 rows. It is recommended to set this parameter
to 8 rows.
A 16-bit timer is used to track the interval between autorefresh burst requests
to the SDRAM. An autorefresh request is issued when the timer reaches a
user-defined value based on the following parameters:
SDRAM frequency
-
Refresh rate
-
Number of SDRAM rows
-
The following formula is used to determine the refresh counter value that
must be programmed in the EMIF fast interface configuration register 1
(EMIFF_SDRAM_CONFIG):
Counter Value +
where T = (1 / traffic controller frequency) and the 400 cycles take into
f
account the worst-case priority scenario where the SDRAM refresh is at
the bottom of the priority queue.
Example: 64-ms refresh rate, 75MHz traffic controller frequency,
4096 rows to be refreshed:
T = 13.3 ns
f
Counter Value +
This ensures a 64-millisecond refresh period for the full SDRAM.
In idle mode, the TC clock is stopped. If the clock will not be restarted for
greater than the maximum refresh period (i.e. 64 ms), the SDRAM should be
placed into the self-refresh mode before the TC enters idle to avoid corruption
of data.
A similar SDRAM data corruption can occur in the event of a warm global
system reset from external device pin. Since the reset event is likely to extend
SDRAM refresh rate
T
f
Number of SDRAM Rows
64000000 ns
* 400
13.3 ns
4096
Memory Interface Traffic Controller
Memory Interfaces
–400
+ 1172 cycles
37