Instruction Cache
Figure 16.
I-Cache RAM Set Tag Registers (RTR1 and RTR2)
RTR1
15
RTR2
15
R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined
Note:
Table 11.
I-Cache RAM Set 1 Tag Register (RTR1) Field Descriptions
Bits
Field
15−0
R1TAG
Table 12. I-Cache RAM Set 2 Tag Register (RTR2) Field Descriptions
Bits
Field
15−0
R2TAG
56
DSP Subsystem
R1TAG
RW-0
R2TAG
RW-0
Value
Description
0000h−
RAM set 1 tag bits. Write a value with zeros in bits 15-12 and the tag in bits
0FFFh
11-0. This register is only applicable if you have selected one or two RAM
sets with the global control register.
Value
Description
0000h−
RAM set 2 tag bits. Write a value with zeros in bits 15-12 and the tag in bits
0FFFh
11-0. This register is only applicable if you have selected one or two RAM
sets with the global control register.
0
0
SPRU890A