I-Cache Status Register (Isr); I-Cache Status Register (Isr) Field Descriptions - Texas Instruments OMAP5910 Reference Manual

4.6.7

I-Cache Status Register (ISR)

Figure 17. I-Cache Status Register (ISR)
15
Note: R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined
Table 13. I-Cache Status Register (ISR) Field Descriptions
Bits Field
15−3 Reserved
2 ENABLE
1−0 Reserved
SPRU890A
The status register contains the ENABLE bit that indicates when the I-Cache
is enabled. When you send an enable request to the I-Cache (CAEN = 1 in the
DSP core status register ST3_55), poll for ENABLE = 1 before writing to either
of the RAM set tag registers.
Reserved
R-0
Value Description
These read-only bits are not used.
I-Cache-enabled bit. When you send an enable request to the
I-Cache, poll for ENABLE = 1 before writing to either of the RAM set
tag registers.
0 The I-Cache is disabled.
1 The I-Cache is enabled.
These bits are not used.
3 2
ENABLE
R-0
DSP Subsystem
Instruction Cache
1 8
Reserved
R-0
57