Physical Address Generation Using Tlb Entry With Size = 11B (Tiny Page) - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
Figure 32.

Physical Address Generation Using TLB Entry with Size = 11b (Tiny Page)

DSP virtual address
Physical address tag
31
Tiny page base address
6.2.2.3 Writing Entries to the TLB
76 DSP Subsystem
23
Tiny page base address
21
Physical address
Four registers (CAM_H_REG,
RAM_L_REG) are used to store the CAM and RAM parts of a TLB entry that
will be written.
The CAM registers hold the virtual address tag, that is, the 14 most significant
bits of the virtual address. Additionally, they contain some status bits that
define whether to preserve the entry upon a TLB global flush operation,
whether the entry is valid or contains only random uninitialized content, and
the size of the memory block (section, large, small, or tiny page) described by
this entry.
The RAM registers hold the physical address tag, that is, the 22 most
significant bits of the physical address. Additionally, they define the access
permissions of the memory region.
A victim pointer identifies the next entry to be written. The same victim pointer
can be used to select an entry to be read. The victim pointer is controlled
through the Lock/Protect Entry Register (LOCK_REG). The Lock/Protect
Entry Register can only be modified by the MPU core when the table walking
logic is disabled.
To write an entry to the TLB, follow these steps:
1) Disable the table walking logic by clearing the TWL_EN bit in the Control
Register (CNTL_REG).
2) Determine CAM and RAM parameters and write them into the CAM and
RAM registers (CAM_H_REG, CAM_L_REG, RAM_H_REG, and
RAM_L_REG).
10 9
Tiny page base address
10 9
CAM_L_REG,
0
Page index
0
0
Page index
RAM_H_REG, and
SPRU890A