Omap5910 Master Block Diagram; Configuration Registers - Texas Instruments OMAP5910 Technical Reference Manual

Figure 1–1. OMAP5910 Master Block Diagram
OMAP5910
32
E
Flash and 16 M
SRAM I
memories F
S
E
16 M
Memory interface
SDRAM
I
traffic controller (TC)
memories
F
F
I
M
I
F
32
32
SRAM
1.5M bits
JTAG/
emulation
I/F
TMS320C55x DSP
(Instruction cache, SARAM
DARAM, DMA,
DSP
32
MMU H/W accelerators)
32
MPU Bus
32
32
32
System
DMA
32
controller
MPU core
16
(TI925T)
(instruction
cache, data
Clock and reset management
cache, MMU)
LCD
I/F
OSC
ETM9
12 MHz
DSP private
Private peripherals
peripheral bus
16
interrupt handlers
DSP public (shared) pheripheral bus
16
16
MPU
Interface
32
MPU
peripheral
32
bridge
32
MPU privatePeripherals bus
32
MPU private peripherals
Level 1/2 interrupt handlers

Configuration registers

OSC
Device identification
Reset External clock
Clock
32 kHz
request
DSP
Timers (3)
DSP public peripherals
Watchdog timer
Level 1/2
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
TIPB
switch
UART3 IrDA
MPU public peripherals
McBSP2
USB Host I/F
MPU public
peripherals bus
USB Function I/F
2
I C
µWire
Camera I/F
MPUIO
32-kHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjstument
counter
Timers (3)
HDQ / 1-WIRE
Watchdog timer
RTC
Introduction
Overview
Mailbox
GPIO I/F
UART1
UART2
1-3