Frame Adjustment Counter - Texas Instruments OMAP5910 Technical Reference Manual

Frame Adjustment Counter

7.16 Frame Adjustment Counter
7.16.1 Features
7-198
The frame adjustment counter counts the number of rising edges of one signal
(start of frame interrupt of the USB function) during a programmable number
of rising edges of a second signal (transit frame synchronization of McBSP2).
This count value can then be used by system-level software to adjust the dura-
tion of the two time domains with respect to each other to reduce overflow and
underflow. If the data being transferred is audio data, this module can be part
of a solution that reduces pops and clicks.
The frame adjustment counter (FAC) is a module that consists of a
frame-synchronization capture pin and a frame-start capture pin. The respec-
tive count values can then be used by system software to adjust the duration
of the two time domains with respect to each other to reduce the overflow and
underflow.
A frame-adjustment reference count register (FARC) is programmed with the
number of frame-synchronization pulses over which the frame-start pulses are
to be counted. A frame-start count register (FSC) is updated with the number
of frame-start rising edges that occur during the programmable FARC period.
A control and configuration register (CTRL) allows you to put the module into
either continuous or halt mode. In continuous mode, the FSC register is
periodically updated with a new value each time the FARC register value is
met, and a new count is automatically initiated. In halt mode, the FSC register
is updated with a new value when the FARC register value is met, counting
halts, and an interrupt is generated. In halt mode, a new count is initiated upon
software servicing the interrupt by reading the FSC register. The RUN bit in the
control and configuration register can enable and disable the counters. If the
RUN bit is set to zero, the counters are reset immediately even though the
count is not finished. The software can use this bit as a software reset. Addi-
tionally, there is a status register (STATUS) containing a FSC_FULL bit that
indicates to system software if FSC has been read subsequent to the last FSC
update.
The main FAC features are:
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Frame-synchronization capture pin (SYNC)
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Frame-start capture pin (START)
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Programmable frame-adjustment reference count register (FARC)
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Read-only frame-start count register (FSC)
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Interrupt generation logic
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Configuration and control register (CTRL)
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Status register (STATUS)