Configuring The I-Cache With The 2-Way Cache And No Ram Set Blocks; Architectural/Operational Description; Software Configuration; System Traffic Considerations - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
4.3 Configuring the I-Cache With the 2-Way Cache and No RAM Set
Blocks
4.3.1

Architectural/Operational Description

4.3.2

Software Configuration

4.3.3

System Traffic Considerations

44 DSP Subsystem
The instruction cache is used to store recently-used instructions stored in DSP
external memory. The I-Cache automatically fills its 2-way cache with
instructions accesses from DSP external memory, in this manner subsequent
accesses are essentially fetched from internal memory.
This section describes how to configure the I-Cache such that the 16KB 2-way
cache is enabled with no RAM set blocks.
When the DSP core fetches an instruction from DSP external memory, the
I-Cache performs an instruction presence check to determine whether the
32-bit requested word is available in the I-Cache. If the instruction is found, the
I-Cache returns the requested instruction to the DSP core; otherwise a DSP
external memory access request is forwarded to the external memory
interface (EMIF). The EMIF passes that request to the DSP Memory
Management Unit (if enabled). After address translation, the DSP MMU places
a request to the traffic controller which accesses shared memory via the
OMAP external memory interfaces (EMIFF and EMIFS).
Follow this procedure to select the 2-way cache and no RAM sets:
1) Write to the appropriate control registers:
a) Write CA0Fh to GCR to indicate N-way cache is used in a 2-way
configuration and that no RAM sets are needed.
b) Write 000Fh to NWCR to initialize the logic for the 2-way cache.
2) Set the cache enable bit (CAEN) bit of DSP core status register ST3_55
to send an enable request to the I-Cache.
3) Poll the I-Cache-enabled (ENABLE) bit of ISR until ENABLE = 1. (The
I-Cache is not instantaneously enabled.)
All DSP subsystem accesses to DSP external memory eventually go through
the traffic controller. The access time for a DSP external memory request will
depend on the amount of competing accesses in the traffic controller as well
as the configurations of the OMAP external memory interfaces (EMIFF and
EMIFS).
SPRU890A