Synchronous Burst Read With - Texas Instruments OMAP5910 Technical Reference Manual

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Memory Interfaces

Figure 4–6. Synchronous Burst Read With Page Alignment

1 TC clock cycles

2 TC clock cycles

FLASH.CS_[X]

FLASH.CS_[X]

Synchronous Burst Read Operation (1/2)

(RDWST+1)xFDIV TC clock cycles

4 TC clock cycles

6 TC clock cycles

Synchronous Burst Read Operation (2/2)

Defined by first access

latency in Flash

configuration register

(RDWST+1)xFDIV TC clock cycles

(RDWST+1)xFDIV TC

Address valid

Data strobing edges

clock cycles

valid on this edge