Dma Global Software Compatibility Register (Dmagscr) - Texas Instruments OMAP5910 Reference Manual

DSP DMA
Table 60. DMA Global Control Register (DMAGCR) Field Descriptions (Continued)
Bits Field
0 MPUI_PRIO
7.3.3

DMA Global Software Compatibility Register (DMAGSCR)

Figure 82. DMA Global Software Compatibility Register (DMAGSCR)
15
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
162 DSP Subsystem
Value Description
MPUI priority bit. MPUI_PRIO assigns the MPUI a high or low priority
level in the service chain of the DMA controller.
Note: When the MPUI has exclusive access to the DARAM and
SARAM ports (MPUI_EXCL = 1), the MPUI priority is irrelevant at
these ports because none of the DMA channels can access the
DARAM and SARAM ports.
0 Low priority level.
1 High priority level.
The global software compatibility register is a 16-bit read/write register that
controls how the DMA controller gets the destination element index and the
destination frame index. The original DMA controller design used one element
index register (DMACEI) for both source and destination, and one frame index
register (DMACFI) for both source and destination. Later designs were
enhanced to allow separate source and destination indexes. In the enhanced
mode:
DMACEI is DMACSEI, the source element index register. DMACFI is
-
DMACSFI, the source frame index register.
The destination element index is stored in a separate destination element
-
index register (DMACDEI) and the destination frame index is stored in a
separate destination frame index register (DMACDEI).
DMAGSCR provides the ability to choose either the original method of
indexing (to maintain software compatibility with code written for the original
design) or the enhanced method of indexing.
DMAGSCR is summarized by Figure 82 and Table 61.
Reserved
R-0
1 0
DINDXMD
RW-0
SPRU890A