Mmu Error Handling - Texas Instruments OMAP5910 Reference Manual

6.2.7

MMU Error Handling

SPRU890A
Notice that the MMU indexes the coarse table as if the entries were specifying
tiny pages. That is, it always selects 1 of 1024 entries. However, the MMU uses
16 bits from the second−level descriptor as a base address for a large page
and 22 bits for a tiny page (see Figure 41 and Figure 43, respectively). This
behavior means that when large pages are used, the descriptor for a large
page must be repeated 64 times in the coarse page table. For similar reasons,
a descriptor for a small page must be repeated 16 times in the coarse page
table.
As described in section 6.2.2, the TLB can be used to bypass the translation
tables. Using this approach, only one TLB entry is required to translate a large
page or a small page.
The following types of faults can occur in the address translation process:
Pre-fetch error.
-
An error occurred during an address-translation pre-fetch request from
the DSP core. The error may have occurred due to a TLB miss or a
translation fault as described below.
TLB miss (table walker disabled).
-
No translation is found in the TLB for the virtual address issued. The
hardware table walker is disabled, and hence the translation cannot be
retrieved from the translation table(s).
Translation fault (table walker enabled).
-
No translation is found for the virtual address required (TLB miss). The
table walker is enabled, but no valid page table entry exists for the given
virtual address.
Permission fault.
-
The section/page access permissions do not match the access type.
When a fault occurs, an interrupt is signaled to the MPU core. The interrupt
service routine (ISR) is then responsible for fault recovery. For example, for a
TLB miss, the ISR might load the missing entry from a page table.
The ISR can determine the cause of the interrupt by reading the fault status
register (FAULT_ST_REG). The virtual address that caused the fault can be
determined by reading the fault address registers (FAULT_AD_H_REG and
FAULT_AD_L_REG).
DSP Memory Management Unit
DSP Subsystem 93