Functional Multiplexing Control 8 Register (Func_Mux_Ctrl_8) - Texas Instruments OMAP5910 Technical Reference Manual

OMAP5910 Configuration Registers
Table 6–36. Functional Multiplexing Control 8 Register (FUNC_MUX_CTRL_8)
Bits Name
31–30 RESERVED
29–27 CONF_ARM_BOOT_R
26–15 RESERVED
14–12 CONF_WIRE_NSCS3_R
11–9 CONF_WIRE_NSCS0_R
8–6 CONF_WIRE_SCLK_R
5–3 CONF_WIRE_SDO_R
2–0 CONF_WIRE_SDI_R
6-38
Description
Reserved for future expansion. These bits must
always be written as 0.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to MPU_BOOT at
reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
Reserved for future expansion. These bits must
always be written as 0.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to UWIRE.CS3 at
reset.
The control for this I/O is forced to 000 at reset and
in compatibility mode.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to UWIRE.CS0 at
reset.
The control for this I/O is forced to 000 at reset and
in compatibility mode.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to UWIRE.SCLK at
reset.
The control for this I/O is forced to 000 at reset and
in compatibility mode.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to UWIRE.SDO at
reset.
The control for this I/O is forced to 000 at reset and
in compatibility mode.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to UWIRE.SDI at
reset.
The control for this I/O is forced to 000 at reset and
in compatibility mode.
Reset
R/W
Value
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0