Sdram Read Single 16-Bit Half-Word With Burst Stop - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Memory Interfaces
Figure 11.

SDRAM Read Single 16-Bit Half-Word With Burst Stop

2
ACCESS_REG
ACCESS_GRANT
COMMAND
ADDRESS
DQ
CURRENT_COL
CURRENT_SIZE
DVALID
SAVE_ADD
LAST_DATE
READ (burst reduced to 1) is interrupted by a STOP command because no new request is pending.
Note:
42
Memory Interface Traffic Controller
ACTV0
READ
STOP
B0/R0
B0/C0
C0+1
C0
0
L = 3
Q
SPRU673

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