Endianism Register (Endianism) - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–25. Endianism Register (ENDIANISM)
Bit Field
31–2 Reserved
1 SWAP
0 EN
Table 4–26. EMIF Fast Interface SDRAM Configuration Register 2
(EMIFF_SDRAM_CONFIG_2)
Bit Field
31–2 Reserved
1 RFRSH_
RST
0 RFRSH_
STBY
The endianism register (ENDIANISM) is used to control endianism conversion
in the DSP memory management unit endianism block.
Value Description
Read is undefined. Writes must be zero.
0 Byte swap (8 bits)
1 Word swap (16 bits)
0 Endianism conversion is disabled (default).
1 Endianism is enabled.
Value Description
Read is undefined. Writes must be zero.
SDRAM self-refresh on warm reset. RFRSH_RST
determines what action the TC SDRAM controller
takes toward setting SDRAM to self-refresh mode
in the event of a warm system reset.
0 SDRAM is not entered to self-refresh mode.
1 SDRAM is entered to self-refresh mode upon warm
system reset.
SDRAM self-refresh on standby. After the TC
receives an idle request from the clock generation
module, RFRSH_STBY determines what action the
TC SDRAM controller takes toward setting SDRAM
to self-refresh mode prior to acknowledging the idle
request.
0 SDRAM enters self-refresh mode.
1 SDRAM enters self-refresh mode prior to the TC
acknowledging an idle request.
Traffic Controller Memory Interface Registers
Memory Interface Traffic Controller
Reset
Access
Value
R All 0
R/W 0
R/W 0
Reset
Access
Value
R All 0
R/W 1
R/W 1
4-55