Dsp I-Cache Input/Output Memory-Mapped Control Registers; System Memory - Texas Instruments OMAP5910 Technical Reference Manual

DSP Memory
Table 3–1. DSP I-Cache Input/Output Memory-Mapped Control Registers
Register Description
ICGR I-cache global control
Reserved Reserved
Reserved Reserved
ICWC I-cache way control
ISR I-cache status
I-cache ½ ramset 1 control
ICRC1
I-cache ½ ramset 1 TAG
ICRTAG1
I-cache ½ ramset 2 control
ICRC2
I-cache ½ ramset 2 TAG
ICRTAG2
3.3.3

System Memory

3.3.4 Memory Map
3-12
Table 3–1 lists the DSP I-Cache I/O-mapped registers.
The DSP has access to all system memory managed by the traffic controller.
External memory space ranges from 0x50000 to 0xFF8000 if the internal
PDROM is enabled, or to 0xFFFFFF if the PDROM is not enabled.
To access memory external to the DSP subsystem, the EMIF issues a memory
access request. The access request is passed through the DSP memory man-
agement unit (MMU), which (if enabled and configured by the MPU) translates
the DSP virtual address into a physical address that is passed to the traffic
controller. The traffic controller completes the access through one of the three
system memory interfaces: internal memory (IMIF), slow external memory
(EMIFS), or fast external memory (EMIFF). If the MMU is not enabled, then the
access request is passed directly to the system traffic controller. In this case,
the DSP virtual addresses are mapped to the first 16M bytes of CS0 of the
system memory.
Figure 3–6 shows the DSP memory space.
Access Word Address
R/W 0x1400
R/W 0x1401
R/W 0x1402
R/W 0x1403
R 0x1404
R/W 0x1405
R/W 0x1406
R/W 0x1407
R/W 0x1408
Reset Value
C006h
0000h
0000h
000Dh
0000h
000Dh
0000h
000Dh
0000h