Time And Calendar Registers And Alarm Register Access - Texas Instruments OMAP5910 Technical Reference Manual

7.13.2.1 Time and Calendar Registers/Alarm Registers
Figure 7–60. Time and Calendar Registers and Alarm Register Access
registers access
TIPB
NSTROBE
BUSY
CLK_32 KHz
Timer counter
7.13.2.2 General Registers
To read or write correct data to and from the time and calendar registers/alarm
registers, the MPU must first poll the BUSY bit of the STATUS register until
BUSY is equal to zero. From this time, and for a time of 15 µs (the available
access period), the MPU can safely access the time and calendar registers/
alarm registers. At the end of the access period, the MPU must restart the
previous sequence. If the MPU accesses the time and calendar registers
outside of the access period, the access is not ensured (see Figure 7–60).
Available TC Available TC
registers access
15 µs
32766
The MPU can access the STATUS_REG and the CTRL_REG at any time
(except the CTRL_REG[5] bit, which must be changed only when the RTC is
stopped).
For the INTERRUPTS_REG, the MPU must respect the available access
period to prevent spurious interrupt.
Read BUSY bit
Forbidden TC
registers access
15 µs
Any read/write TC registers access
32767
RTC update
Real-Time Clock
Available TC
registers access
15 µs
0
MPU Public Peripherals
1
7-171