Receive Control Register 1 Configuration (Dsp_Write(0X00A0) => Rcr1); Receive Control Register 2 Configuration (Dsp_Write(0X80A1) => Rcr2); Transmit Control Register 1 Configuration (Dsp_Write(0X00A0) => Xcr1) - Texas Instruments OMAP5910 Technical Reference Manual

9.3.4.3 Receive Control Register Configuration
Table 9–6. Receive Control Register 1 Configuration (DSP_Write(0x00a0) => RCR1)
Bit Config Value
15 0b
14–8 000 0000b
7–5 101b
4–0 0 0000b
Table 9–7. Receive Control Register 2 Configuration (DSP_Write(0x80a1) => RCR2)
Bit Config Value
15 1b
14–8 000 0000b
7–5 101b
4–3 00b
2 0b
1–0 01b
9.3.4.4 Transmit Control Register Configuration
Table 9–8. Transmit Control Register 1 Configuration (DSP_Write(0x00a0) => XCR1)
Bit Config Value
15 0b
14–8 000 0000b
7–5 101b
4–0 0 0000b
DSP_Write(0x00a0) => RCR1; set up RCR1 as shown in Table 9–6.
Description
Reserved
Set receive frame length as one word per frame
Set receive word length as 32 bits per frame
Reserved
DSP_Write(0x80a1) => RCR2; set up RCR2 as shown in Table 9–7.
Description
Set dual-phase frame
Set receive frame length as one word per frame
Set receive word length as 32 bits per frame
Don't care for single-phase frame
Set FSR not ignore after the first resets the transfer
Set data delay as 1 bit
DSP_Write(0x00a0) => XCR1; set up XCR1 as shown in Table 9–8.
Description
Reserved
Set transmit frame length as one word per frame
Set receive word length as 32 bits per frame
Reserved
DSP Public Peripherals
McBSP1
9-9