Lcd Dual-Frame Mode Transfer Scheme - Texas Instruments OMAP5910 Technical Reference Manual

Table 5–8. IMIF LCD Register Settings—Two Frames (Continued)
Figure 5–12. LCD Dual-Frame Mode Transfer Scheme
DMA_LCD_CTRL
DMA_LCD_TOP_F1_L
DMA_LCD_BOT_F1_U
DMA_LCD_BOT_F1_L
DMA_LCD_TOP_F2_U
DMA_LCD_TOP_F2_L
DMA_LCD_BOT_F2_U
DMA_LCD_BOT_F2_L
The transfer starts when the enable (hardware) signal from the LCD controller
is asserted high.
The transfer runs, and the interrupts are generated at the ends of frames 1
and 2.
IMIF
Video frame 1
Video frame 2
When an interrupt occurs, read the DMA_LCD_CTRL register to find the
source of the interrupt.
If DMA_LCD_CTRL(3) = 1, end frame 1 interrupt.
If DMA_LCD_CTRL(4) = 1, end frame 2 interrupt.
When bottom of frame 1 is reached, the DMA loads the top frame 2 addresses.
When bottom of frame 2 is reached, the DMA loads the top frame 1 address.
Reset DMA_LCD_CTRL3 and 4 and wait for another interrupt.
0x0B 0000
0x0B 00DE
DMA
0x0C 0000
0x0C 00DE
System DMA Controller
LCD Dedicated Channel
Register Settings
0x0000
0x000B
0x00DE
0x000C
0x0000
0x000C
0x00DE
LCD
controller
5-31