Level 2 Interrupt Control Flow - Texas Instruments OMAP5910 Technical Reference Manual

Interrupt Handlers
Figure 8–4. Level 2 Interrupt Control Flow
T
I
P
B
8-18
16 incoming interrupts
Edge dectection flip_flops
Edge or level direction
Interrupt input register (IIR)
Interrupt set register (ISR)
OR
Mask interrupt register (MIR)
Interrupt level register 0 (ILR0)
Interrupt level register 1 (ILR1)
Interrupt level register 16 (ILR16)
SIR_IRQ
Binary coded source IRQ reigster
SIR_FIQ
Binary coded source RIQ register
Process next pending IRQ
Process next pending FIQ
Generate IRQ
Generate FIQ
FIQ
To DSP level 1
Interrupt handler