Dsp Subsystem Memory Interface; Functional Block Diagram - Texas Instruments OMAP5910 Reference Manual

6.1.3

Functional Block Diagram

Figure 23.

DSP Subsystem Memory Interface

6.1.4 Supported Usage of the DSP MMU
SPRU890A
Figure 23 shows the role of the DSP MMU within the DSP subsystem memory
structure.
OMAP device
DSP subsystem
Requestors
DMA
DSP core
data buses
DSP core
program buses
There are two ways to use the MMU:
The contents of the TLB can be written manually by the MPU core.
-
Using this approach does not require any translation tables. However, the
MPU core has to update the TLB when no valid address translation is
found (TLB miss).
The MMU table walking logic can be enabled to automatically update the
-
TLB by reading a structure of translation tables.
The translation table structure has to be set up by the MPU core before the
MMU is enabled. However, no action from the MPU core is required on a
TLB miss.
You can also combine these two options. For instance, the MPU core can set
up time-critical translations in the TLB and other non-time-critical address
translations in translation tables, which the table walking logic reads later. The
DSP MMU can also be disabled, in which case all DSP subsystem external
memory requests would be mapped to the first 16M-bytes of OMAP system
memory (CS0).
Sections 6.3 and section 6.4 give more detail on using one of these two
supported usage options.
DSP Memory Management Unit
DSP MMU
Addr. Addr.
Address
conversion
Data Data
Endianess
conversion
Access
checking
Resources
IMIF
Internal
SRAM
Traffic
controller
EMIFS
Flash
EMIFF
SDRAM
DSP Subsystem 67