Interrupt Handler Level 1 And Level 2 Registers - Texas Instruments OMAP5910 Technical Reference Manual

Interrupt Handler Level 1 and Level 2 Registers

6.6 Interrupt Handler Level 1 and Level 2 Registers
Table 6–17. Interrupt Handler Registers
Name Description
ITR Interrupt input
MIR Mask interrupt
SIR_IRQ_CODE Interrupt encoded source (IRQ)
SIR_FIQ_CODE Interrupt encoded source (FIQ)
CONTROL_REG Interrupt control register
ILR0 Interrupt priority level for IRQ 0
ILR1 Interrupt priority level for IRQ 1
ILR2 Interrupt priority level for IRQ 2
ILR3 Interrupt priority level for IRQ 3
ILR4 Interrupt priority level for IRQ 4
ILR5 Interrupt priority level for IRQ 5
ILR6 Interrupt priority level for IRQ 6
ILR7 Interrupt priority level for IRQ 7
ILR8 Interrupt priority level for IRQ 8
ILR9 Interrupt priority level for IRQ 9
ILR10 Interrupt priority level for IRQ 10
ILR11 Interrupt priority level for IRQ 11
ILR12 Interrupt priority level for IRQ 12
ILR13 Interrupt priority level for IRQ 13
ILR14 Interrupt priority level for IRQ 14
6-20
There are two sets of interrupt handler registers: one for the level 1 handler,
the other for the level 2 handler (see Table 6–17). Table 6–18 through
Table 6–24 describe the register bits.
Base address for interrupt handler 1: FFFE:CB00
Base address for interrupt handler 2: FFFE:0000
Bit width: 32 bits
R/W Bits Offset
R/W 32 bits 0X00
R/W 32 bits 0X04
R 5 bits 0X10
R 5 bits 0X14
R/W 2 bits 0X18
R/W 7 bits 0X1C
R/W 7 bits 0X20
R/W 7 bits 0X24
R/W 7 bits 0X28
R/W 7 bits 0X2C
R/W 7 bits 0X30
R/W 7 bits 0X34
R/W 7 bits 0X38
R/W 7 bits 0X3C
R/W 7 bits 0X40
R/W 7 bits 0X44
R/W 7 bits 0X48
R/W 7 bits 0X4C
R/W 7 bits 0X50
R/W 7 bits 0X54
Reset
Value
0x0000 0000
0xFFFF FFFF
0x00
0x00
0x0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00