Interrupt Source Status Register (It_Status) - Texas Instruments OMAP5910 Technical Reference Manual

Table 7-4. Clock Control Register (CTRLCLOCK) (Continued)
Bit Name
4 CAMEXCLK_EN
3 POLCLK
2-0 FOSCMOD
Table 7-5. Interrupt Source Status Register (IT_STATUS)
Bit Name
31-6 RESERVED
5 DATA_TRANSFER
4 FIFO_FULL
3 H_DOWN
2 H_UP
1 V_DOWN
0 V_UP
Value Function
0 Disables
1 Enables CAM.EXCLK
Sets polarity of CAM.LCLK
0 Data latched on rising edge
1 Data latched on falling edge
Sets the frequency of the CAM.EXCLK clock
000 12 MHz
010 6 MHz
100 9.6 MHz (48 MHz/5)
101 24 MHz (48 MHz/2)
110 8 MHz (48 MHz/6)
Function
Reserved bits
Data transfer status. Set to 1 when trigger is reached.
Reset by reading IT_STATUS if no event in the meantime.
Detect rising edge on FIFO full flag. Reset by reading
IT_STATUS if no event in the meantime.
Flag for horizontal synchronous falling edge occurred.
Reset by reading IT_STATUS if no event in the meantime.
Flag for horizontal synchronous rising edge occurred.
Reset by reading IT_STATUS if no event in the meantime.
Flag for vertical synchronous falling edge occurred. Reset
by reading IT_STATUS if no event in the meantime.
Flag for vertical synchronous rising edge occurred. Reset
by reading IT_STATUS if no event in the meantime.
Camera Interface
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
MPU Public Peripherals
Reset
Value
0x0
0x0
0x00
Reset
Value
0xX
0x0
0x0
0x0
0x0
0x0
0x0
7-13