Image Data Transfer - Texas Instruments OMAP5910 Technical Reference Manual

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Figure 7-3. Image Data Transfer

Camera Data Validation

The incoming byte on CAM_D can be latched on the rising or falling edge of

CAM.LCLK generated by the camera itself. The POLCLK bit can select the

polarity of CAM.LCLK in the clock control register.

Program the camera interface so that data is always captured opposite the

launch edge. For example, if data is latched by the sensor on the rising edge

of CAM.LCLK, configure the interface to catch the data on the falling edge of

The high level of the vertical synchronous and horizontal synchronous signals

indicates that the data is valid on CAM_D. This level is registered in VSTATUS

and HSTATUS, which are updated on edge detection of vertical and horizontal

synchronous signals.

It is possible to gate the clock during the VSYNC and/or HSYNC blanking peri-

ods. However it is recommended to let the clock run, because there is a pro-

cess based on LCLK that clears all internal resynchronization registers while

VSYNC or HSYNC is low before starting a new line or a new image. This mech-

anism prevents the FIFO from remaining word, which could corrupt the data

of a new line.

Camera Interface

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MPU Public Peripherals