Interpreting Access Permission - Texas Instruments OMAP5910 Technical Reference Manual

2.7.10 Permission Access
Table 2–25. Interpreting Access Permission
Domain AP S
x0 xx x
01 00 0
01 00 1
01 00 0
01 00 1
01 01 x
01 10 x
01 11 x
01 xx 1
11 xx x
† In client mode, the combination S/R = 11 is reserved and generates a permission fault. Therefore, on these three lines, S/R can
only take the values 00, 01, or 10.
2.7.11 Fault Checking Sequence
Both instructions and data need access permission checks, but their respec-
tive access violations are handled differently. A data access error generates
a DABORT and stores the status, domain, and address in FSR and FAR. An
instruction fetch generates an IABORT only; it does not update FSR and FAR
as it is possible the aborted instruction is not executed (if it is branched
around). The IABORT flags the instruction as it enters the TI925T.
When the MMU is turned off, the physical address is output directly and no
memory access permission checks are performed.
R Supervisor User
x No access No access
0 No access No access
0 Read only No access
1 Read only Read only
1 Reserved Reserved
x Read/write No access
x Read/write Read only
x Read/write Read/write
1 Reserved Reserved
x Full access Full access
The sequence by which the MMU checks for access faults is slightly different
for sections and pages. Figure 2–20 illustrates the sequence for both. The
following sections describe the conditions that generate each of the faults.
MPU Memory Management Unit
Description
Generates a domain fault
Generates a permission fault
Supervisor read only permitted
Any write generates a permission fault.
Generates a permission fault
Access allowed only in supervisor mode.
User writes cause a permission fault.
All accesses are allowed.
Generates a permission fault
No permission fault can be generated.
MPU Subsystem
†
†
†
2-43