DSP Memory Management Unit
Table 2–32. Fault Status Register (F_ST_REG)) – Offset Address (hex): 14
Bit
Function
15–4
Reserved
3
Error occurred during a prefetch. Active high.
2
Permission fault. Active high.
1
TLB miss. Active high.
0
Translation fault. Active high.
Table 2–33. IT Acknowledge Register (IT_ACK_REG) – Offset Address (hex): 18
Bit
Function
15–1
Reserved
0
Write a 1 to this bit to acknowledge the interrupt. A write of 0 has
no effect; a write of 1 clears the bit automatically.
Table 2–34. TTB Register MSB (TTB_H_REG) – Offset Address (hex): 1C
Bit
Function
15–0
MSB of TTB
Table 2–35. TTB Register LSB (TTB_L_REG) – Offset Address (hex): 20
Bit
Function
15–7
LSB of TTB
6–0
Reserved
2-50
Value at
Hardware
Reset
Size
Access
12
1
R
1
R
1
R
1
R
Value at
Hardware
Size
Access
Reset
15
1
W
Value at
Hardware
Size
Access
Reset
16
R
Value at
Hardware
Reset
Size
Access
9
R
7
0
0
0
0
0
0
0