Validity - Texas Instruments OMAP5910 Technical Reference Manual

Table 2–1. Data Cache Configuration (Continued)
C_CP15 C_MMU
1 1
1 1
Note: The load multiple instruction does not perform a burst read.
2.4.2

Validity

B_MMU Functional Description
0 Cache search active: write through mode (WT)
• Read hits do not generate external accesses.
• Write hits update the cache and the external memory.
• Read misses cause a line load.
• Write misses generate external accesses.
1 Cache search active: copy-back mode (CB)
• Read and write hits do not perform external accesses.
• Read misses cause a line load.
• Write misses do not update the cache, and they generate an external
access.
If C_CP15 = 0, the D-cache is disabled and it is not searched. If a memory
region is changed from cacheable to noncacheable and data must come from
external memory, the cache must be flushed.
The D-cache always requires that the MMU be enabled, so virtual addresses
are always in use. The TLB descriptors in memory can be cached or not
cached. When software is switching virtual address maps, take care to
invalidate the data cache so that the wrong data value is not returned (that is,
so that a false D-cache hit does not occur). To do this, the CP15 register allows
software to invalidate the entire D-cache. As noted before, disabling the
D-cache and reenabling it does not invalidate it.
If CB mode is used (see Table 2–1), software must first clean the cache to
make it coherent with main memory (this is not necessary in WT mode,
because main memory is continuously updated as the data cache is used).
For CB mode, the VIVT algorithm must be used if software is to avoid missing
interrupts during the clean operation. Timer interrupts, for example, can be
missed.
To avoid this problem, the hardware clean operation can be interrupted, so the
software algorithm must check the min/max registers (CP15 registers) to
determine if the clean operation has completed. If not, it must repeat the
operation until complete.
Data Cache
MPU Subsystem 2-7