Format Of The I_Min And I_Max Registers; Format Of The Thread-Id Register; Ti925T_Status Register - Texas Instruments OMAP5910 Technical Reference Manual

Figure 2–8. Format of the I_min and I_max Registers
31
31
Figure 2–9. Format of the Thread-ID Register
31
UNP/SBZ
Table 2–15. TI925T_status Register
Bit Name
31 dcache_dirty
4 S_abort
3 dtlb_mode
2 Itlb_mode
1 wb_full
0 buffered_write_aborted
UNP/SBZ
UNP/SBZ
I_max indicates the maximum index of the data cache containing a dirty line.
I_min indicates the minimum index of the data cache containing a dirty line.
Upon reset, D-cache flush or end of the full D-cache clean, the value of I_max
is cleared and the value of all the I_min bits is set to 1.
The TI debugger uses this register to support multithread debug capability.
Function
When at 1, indicates the data cache may contain lines marked as dirty.
When at 1, indicates that external abort occurred. This bit is set to zero
upon reset and when read by TI925T.
When at 1, indicates that DTLB counter is in random mode.
Default is set to sequential mode. This bit is set to zero upon reset.
When at 1, indicates that ITLB counter is in random mode.
Default is set to sequential mode. This bit is set to zero upon reset.
When at 1, indicates that write buffer is full. This bit is set to zero upon
reset.
Set to one by the hardware when the system bus controller receives an
s_abort following external write from the WB. This is simply an indication
for the debug. This bit is set to zero upon reset and when read by TI925T.
Y
Y
16 15
Coprocessor 15
Z
l_min UNP/SBZ
Z
l_max UNP/SBZ
Thread ID
MPU Subsystem
0
0
16
2-25