McBSP2
7.10.1.12
Receive Control Register Configuration
Table 7–86. Receive Control Register 1 Configuration
Configuration
Bit
Value
15
0b
14–8
000 0000b
7–5
010b
4–0
0 0000b
Table 7–87. Receive Control Register 2 Configuration
Configuration
Bit
Value
15
0b
14–8
000 0000b
7–5
000b
4–3
00b
2
0b
1–0
01b
7.10.1.13
Transmit Control Register Configuration
Table 7–88. Transmit Control Register 1 Configuration
Configuration
Bit
Value
15
0b
14–8
000 0000b
7–5
010b
4–0
0 0000b
7-114
ARM_Write(0x0040) => RCR1; set up RCR1 per below configuration.
Description
Reserved
Set receive frame length as one word per frame
Set receive word length as 16 bits per frame
Reserved
ARM_Write(0x0001) => RCR2; set up RCR2 per below configuration.
Description
Set single-phase frame
Set receive frame length as one word per frame
Don't care for single-phase frame
Don't care for single-phase frame
Set FSR not ignore after the first resets the transfer
Set data delay as 1 bit
ARM_Write(0x0040) => XCR1; set up XCR1 per below configuration.
Description
Reserved
Set transmit frame length as one word per frame
Set transmit word length as 16 bits per frame
Reserved