Mmu Interrupt Acknowledge Register (It_Ack_Reg); Mmu Translation Table Registers (Ttb_H_Reg, Ttb_L_Reg) - Texas Instruments OMAP5910 Reference Manual

Table 28. MMU Interrupt Acknowledge Register (IT_ACK_REG) Field Descriptions
Bits Field
31−1 Reserved
0 IT_ACK
6.5.8

MMU Translation Table Registers (TTB_H_REG, TTB_L_REG)

Figure 54. MMU Translation Table Registers (TTB_H_REG, TTB_L_REG)
TTB_H_REG
31
Reserved
TTB_L_REG
31
15
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
SPRU890A
Value Description
These bits are not used.
The MPU core must write a 1 to this bit to acknowledge the interrupt
from the DSP MMU.
0 Writing 0 has no effect.
1 Writing a 1 to this bit acknowledges the interrupt from the DSP MMU.
These registers together specify the base address of the first-level translation
table. The base address corresponds to the 25 most-significant bits of the
32-bit address of the first-level translation table.
Note:
TTB_H_REG and TTB_L_REG can only be modified by the MPU core when
the table walking logic is disabled.
16
R-0
TTB_L
RW-0
15
Reserved
R-0
7
DSP Memory Management Unit
TTB_H
RW-0
6
Reserved
R-0
DSP Subsystem
0
16
0
109