Dma Global Timeout Control Register (Dmagtcr); Dma Global Software Compatibility Register (Dmagscr) Field Descriptions - Texas Instruments OMAP5910 Reference Manual

Table 61. DMA Global Software Compatibility Register (DMAGSCR) Field Descriptions
Bits Field
15−1 Reserved
0 DINDXMD
7.3.4

DMA Global Timeout Control Register (DMAGTCR)

Figure 83. DMA Global Timeout Control Register (DMAGTCR)
15
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
SPRU890A
Value Description
These read-only bits return 0s when read.
Destination element and frame index mode bit. This bit determines
which registers will be used to indicate the destination element and
frame indexes.
0 Compatibility mode.
One element index for both the source and destination is stored in the
channel source element index register (DMACSEI).
One frame index for both the source and destination is stored in the
channel source frame index register (DMACSFI).
1 Enhanced mode.
The source element index is stored in the channel source element
index register (DMACSEI).
The destination element index is stored in the channel destination
element index register (DMACDEI).
The source frame index is stored in the channel source frame index
register (DMACSFI).
The destination frame index is stored in the channel destination frame
index register (DMACDFI).
The global timeout control register (see Figure 83 and Table 62) is a 16-bit
read/write register that enables or disables timeout counters on the SARAM
and DARAM ports. If the timeout counters are disabled, the DMA controller will
never generate a timeout error for these ports. For details about the timeout
error conditions, see section 7.2.15.3.
Reserved
R-0
2 1
DTCE
RW-0
DSP Subsystem
DSP DMA
0
STCE
RW-0
163