Sdram Write Burst 32-Bit Word Followed By Read Burst 8 Half-Word - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
Figure 13.

SDRAM Write Burst 32-Bit Word Followed by Read Burst 8 Half-Word

ACCESS_REG
2
ACCESS_GRANT
COMMAND
ADDRESS
DQ
CURRENT_COL
CURRENT_SIZE
DVALID
SAVE_ADD
LAST_DATE
WRITE (burst reduced to 2) is interrupted by a READ request pending on a bank and row already active.
Note:
44 Memory Interface Traffic Controller
ACTV0 WRITE READ
2
B0/R0 B0/C0 B1/C1
D D
C0+1 C1+2
C0 C0+1
1 0
L = 3
Q Q
Ignored
C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
C1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6
7 6 5 4 3
STOP
Q Q Q Q Q
C1+8
C1+7
2 1 0
Q
SPRU673