Level 1 Interrupt Mapping; Level 1 Interrupts - Texas Instruments OMAP5910 Technical Reference Manual

Interrupt Handlers
8.4.1

Level 1 Interrupts

Table 8–21. Level 1 Interrupt Mapping
Level 1 Interrupt
RESET
NMI
Emulator/Test
Level-2 INTH FIQ
TC_ABORT
MAILBOX 1
Reserved
GPIO
TIMER3
DMA_channel_1
MPU
Reserved
UART
WDGTIMER
DMA_channel_4
DMA_channel_5
EMIF
Local Bus
8-16
The DSP level 1 interrupt controller receives interrupts from peripherals and
sends them to the DSP core (see Table 8–21). The TI peripheral bus is respon-
sible for prioritizing, capturing, and synchronizing interrupts, before sending
them to the DSP. The level 1 interrupt controller has a nonmaskable interrupt
(NMI) and 22 maskable interrupts. Of the 22 maskable interrupts, 21 are
peripheral interrupts and the remaining one is an MPU interrupt.
Level 1 DSP interrupts must be at least two DSP_CLK cycles long in order for
the DSP to recognize it. To ensure that this requirement is met, the DSP is pro-
vided with and internal hardware module called the DSP interrupt interface
(described in Section 8.5).
Priority
0
1
3
5
6
7
9
10
11
13
14
15
17
18
21
22
4
8
DSP Vector
Interrupt Location
FFFF00
FFFF08
INT2 FFFF10
INT3 FFFF18
INT4 FFFF20
INT5 FFFF28
INT6 FFFF30
INT7 FFFF38
INT8 FFFF40
INT9 FFFF48
INT10 FFFF50
INT11 FFFF58
INT12 FFFF60
INT13 FFFF68
INT14 FFFF70
INT15 FFFF78
INT16 FFFF80
INT17 FFFF88
DSP
IFR_bit/IMT_bit (26:0)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17