Emif To Lcd Register Settings-One Frame; Dma_Lcd_Top_F1_L; Dma_Lcd_Top_F1_U; Dma_Lcd_Bot_F1_L - Texas Instruments OMAP5910 Technical Reference Manual

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EMIFF to LCD, One Frame

Table 5–7. EMIF to LCD Register Settings—One Frame

to continue until the LCD enable signal (dma_lcd_en) is disabled one time

(LCDEN = 0). This mechanism is provided to avoid having dummy high-priority

requests to the ports because the LCD channel's frame data flow has been

corrupted. If the LCD controller loses the flow, it should send a software inter-

rupt to cause the MPU to quickly stop the current transfer. The transfer is

allowed to run normally after the dma_lcd_en is asserted again (LCDEN = 1).

Figure 5–11 shows a transfer for a video frame located in EMIFF to the LCD

controller. The size for the LCD display is 6 x 16 pixels with 16 bits per pixel.

So the length of the video frame is:

6 x 16 x 2 (in bytes) + 32 bytes for the palette = 224 bytes

If the video frame starts at address 0x0B0000, the bottom address of the video

frame is 0x0B00DE.

Registers settings are shown in Table 5–8.

DMA_LCD_CTRL

Bus_error_ie

The transfer starts when the enable (hardware) signal from the LCD controller

is asserted high.

LCD Dedicated Channel

0 (one frame)

System DMA Controller