Dma Channel Status Register (Dma_Csr) - Texas Instruments OMAP5910 Technical Reference Manual

Table 5–14. DMA Channel Interrupt Control Register (DMA_CICR) (Continued)
Bit Name
0 TOUT_IE
Table 5–15. DMA Channel Status Register (DMA_CSR)
Bit Name
15–14 RESERVED
13–7 ALT_STATUS
Value Description
Time-out interrupt enable
0 The DMA does not send an interrupt to the processor if
a time-out error occurs.
1 The DMA sends an interrupt to the processor if a
time-out error occurs either in the source or in the
destination port of the channel.
The interrupt enable bits are used to choose the events that cause the DMA
channel to send an interrupt to the processor. There are two classes of events:
-
Error events: errors during the transfer (time out, event drop)
-
Status events: new frame starts, end of data block to transfer is reached.
Each time an event occurs, if the corresponding interrupt enable bit is set, the
channel sends an interrupt to the processor. At the same time, the correspond-
ing status bit is set in DMA_CSR (DMA channel status register) or in
DMA_TSR ( DMA time-out error status register ). A status bit is not set if the
corresponding interrupt enable bit in DMA_CICR equals 0.
Value Description
Alternate status bits for channels with shared
interrupts. For DMA channels with shared
interrupts, these seven bits have the same
function as bits 6–0 of this register, except they
correspond to the other channel that shares the
interrupt. For example, in register
DMA_CSR_CH0, these bits correspond to
channel 6 status and mirror the values present in
DMA_CSR_CH6[6–0]. DMA_CSR registers for
both channel 0 and 6 are cleared when either
register is read. For channels without shared
interrupts, these bits are reserved.
Type
RW
Type
System DMA Controller
Registers
Reset
Value
1
Reset
Value
0000000
5-49