Level 1 Coarse Page Table Descriptor; Level 1 Section Descriptor - Texas Instruments OMAP5910 Technical Reference Manual

Table 2–19. Level 1 Coarse Page Table Descriptor
Bit Name
31–10 COARSE_PG_BASE
9 RESERVED
8–5 DOMAIN
4 RESERVED
3–2 RESERVED
1–0 RESERVED
Table 2–20. Level 1 Section Descriptor
Bit Name
31–20 SECTION_BASE
19–12 Reserved
11–10 AP
9 Reserved
8–5 DOMAIN
4 Reserved
3 C
2 B
Function
Base address used to access the coarse page table entry. The coarse
page table index selecting an entry is derived from the virtual address. If a
page table descriptor is returned from the level 1 fetch (Bit 0 = 1), a level
2 fetch is initiated.
Reserved. Must always be written to as 0.
Specify which one of the 16 domains (held in the domain access control
register) contains the primary access controls.
Reserved. Must be written to as 1 for backward compatibility.
Reserved. Must be written as 0.
Reserved. Must be written as 1.
Function
The 12 MSBs of the address of the section in physical memory (section
base address).
Must always be written to as 0.
Specify the access permissions for this section (see Table 2–24).
Must always be written to as 0.
Specify which one of the 16 domains (held in the domain access control
register) contains the primary access controls.
Must be written to as 1 for backward compatibility.
Cacheable (C_MMU): indicates that data or instructions at this address
are placed in the cache if the cache is enabled.
Bufferable (B_MMU): indicates that data writes at this address are
buffered if the write buffer is enabled.
MPU Memory Management Unit
MPU Subsystem 2-33