Hdq And 1-Wire Overview; Power-Down Mode - Texas Instruments OMAP5910 Technical Reference Manual

HDQ and 1-Wire Protocols

7.15.2 Power-Down Mode

7.15.3 HDQ and 1-Wire Battery Monitoring Serial Interface
Figure 7–70. HDQ and 1-Wire Overview
MPU TIPB
(public)
Interrupt
7-194
Writing to the appropriate bit in the control and status register shuts the clock
to the state machine. The state machines are reset when the clock is disabled,
and if any transaction is being performed it is aborted into the reset state. The
register values are not affected by disabling the clock. No register access must
be performed to the module registers after the software puts the module in
power-down mode (by setting bit 5 of the control and status register to 0) other
than a write to the power-down bit to take it out of power-down mode.
The HDQ and 1-Wire battery monitoring serial interface module implements
the hardware protocol of the master function of the TI/Benchmarq HDQ and
the Dallas Semiconductor 1-Wire protocol. The module works off a command
structure that is programmed into transmit command registers. The received
data is in the received data register. The firmware is responsible for doing the
correct sequencing in the command registers. The module only implements
the hardware interface layer of the protocols.
The HDQ and the 1-Wire mode are selectable in software, which must be done
before any transmit and receive from the module is performed. The mode is
assumed static during operation of the device.
OMAP5910
0
HDQ / 1-wire
Pin multiplexing for
OMAP5910
GPIO11 device pin
TI
BQxxxx
device