Wait States - Texas Instruments OMAP5910 Technical Reference Manual

TIPB Bridge
Table 3–8. Wait States
3-30
3) DMA
If CPU_Priority = 0, the CPU, MPUI, and DMA accesses to the TIPB bridge
are arbitrated in rotating priority fashion.
-
Wait state bits for strb1 and strb2
Strb1 field sets the access rate for the following peripherals:
J
TIPB registers
J
CLKM2 registers
Strb2 field sets the access rate for the following peripherals:
J
UART3 (test)
J
McBSP1 (audio PCM)
J
McBSP3 (optical)
J
MCSI-1
J
MCSI-2
J
GPIO
J
Mailbox
J
DSP MPUI register
The control mode register bits [5–3] and [8–6] contain the number of wait
states required to generate the appropriate strobe frequency (see Table 3–8).
Number of

Wait States

0
1
2
3
4
5
6
7
Strobe Period
DSP clk/2
DSP clk/3
DSP clk/4
DSP clk/5
DSP clk/6
DSP clk/7
DSP clk/8
DSP clk/9