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Texas Instruments OMAP36 Series Manuals
Manuals and User Guides for Texas Instruments OMAP36 Series. We have
1
Texas Instruments OMAP36 Series manual available for free PDF download: Technical Reference Manual
Texas Instruments OMAP36 Series Technical Reference Manual (3738 pages)
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 24.86 MB
Table of Contents
Table of Contents
58
Omap36Xx High-Tier Environment
190
Omap36Xx High-Tier Block Diagram
191
POP Concept
197
Stacked Memory Package on the POP Device
197
Stacked Memory Package on the POP Device
198
Summary of Memories Supported by the POP Interface
198
Omap36Xx Packages
199
Device Features
199
Device Identification Registers
201
CONTROL_IDCODE Register Definition
202
Hawkeye Number Value
202
Revision Number Value
202
CONTROL_IDCODE Register Value
202
CONTROL_PRODUCTION_ID Register Silicon Type Identification
202
Interconnect Overview
205
Global Memory Space Mapping
207
L3 Control Register Mapping
209
L4-Core Memory Space Mapping
211
L4-Wakeup Memory Space Mapping
213
L4-Peripheral Memory Space Mapping
214
L4-Emulation Memory Space Mapping
215
Register Access Restrictions
216
IVA2.2 Subsystem Memory Hierarchy
219
L1D RAM Cache Allocation Example (L3 Interconnect View)
220
IVA2.2 Immu Address Translation
221
L3 Interconnect View of the IVA2.2 Subsystem Memory Space
221
DSP View of the IVA2.2 Subsystem Memory Space
222
EDMA View of the IVA2.2 Subsystem Memory Space
223
Comparison of Energy Consumption With/Without DVFS
226
Introduction to Power Managements
226
Smartreflex Example
227
Comparison of Energy Consumed With/Without DPS
228
Performance Level and Applied Power-Management Techniques
230
Generic Clock Domain
231
Generic Power Domain
231
States of a Clock Domain
231
Generic Voltage Domain
233
Voltage, Power, and Clock Domain Hierarchical Architecture
234
Functional and Interface Clocks
235
Smartreflex Voltage-Control Functional Overview
237
PRCM Overview
239
PRCM Overview
240
PRCM Functional External Interface (Detailed View)
242
PRCM Environment
242
External Clock Interface
243
External Clock Signals
243
PRCM External Clock Sources
244
External Reset Signals
245
Power Control Interface for External Power IC
245
Power Control Interface
245
PRCM Integration
246
PRCM Integration
247
Device Power Domains
248
PRCM Power Domains
249
PRCM Reset Signals
249
PRCM Reset Signals
250
Reset Manager Interface with Generic Power Domain
251
Overview
251
PRCM Functional Description
251
Reset Sources Overview
253
Global Reset Sources
253
Local Reset Sources
254
Reset Destination Overview
255
MPU Power Domain Reset Signal
256
NEON Power Domain Reset Signal
256
IVA2 Power Domain Reset Signals
256
CORE Power Domain Reset Signals
256
DSS Power Domain Reset Signal
257
CAM Power Domain Reset Signal
257
USBHOST Power Domain Reset Signal
257
SGX Power Domain Reset Signal
257
WKUP Power Domain Reset Signals
258
PER Power Domain Reset Signal
258
Smartreflex Power Domain Reset Signal
258
DPLL Power Domain Reset Signals
258
External Warm Reset Interface
259
EFUSE Power Domain Reset Signal
259
BANDGAP Logic Reset Signal
259
Device Reset Manager Overview
261
Power Domain Reset Management: Part
262
Power Domain Reset Management: Part
263
Power Domain Reset Management: Part
264
Global Reset Summary
265
Local Reset Summary
266
Power-Up Sequence
268
Resets
268
Warm Reset Sequence
271
IVA2.2 Subsystem Power-Up Reset Sequence
273
IVA2 Software Reset Sequence
275
IVA2 Global Warm Reset Sequence
277
IVA2 Power Domain Power Transition Reset Sequence
279
Power Control Overview
282
Power Domain Modules
283
Power Domain States
285
Domain Power Control Summary
286
PRCM Clock Manager Overview
292
External Clock I/O
293
System Clock Input Configurations
293
External Clock I/Os
294
Internal Clock Sources
295
PRM Clock Generator
297
CM Clock Generator Functional Overview
299
Generic DPLL Functional Diagram
301
DPLL3 Clocks
303
DPLL5 Clocks
304
DPLL4 Functional Diagram
305
DPLL4 Clocks
306
Low-Jitter DPLL Output Clocks
308
Other DPLL Output Clocks
308
Source-Clock Summary
308
MPU Power Domain Clocking Scheme
309
IVA2 Power Domain Clocking Scheme
310
SGX Power Domain Clocking Scheme
311
CORE Clock Signals: Part
312
CORE Clock Signals: Part
313
CORE Clock Signals: Part
314
EFUSE Clock Signals
315
DSS Clock Signals
316
CAM Clock Signals
317
USBHOST Clock Signals
318
Cm_Fclken_Usbhost
318
WKUP Clock Signals
319
PER Clock Signals
320
SMARTREFLEX Clock Signals
321
DPLL Clock Signals
322
Clock Distribution
323
Mode)
324
Peripheral Module Functional Clock Frequencies
325
Sys_Clkreq Pad Direction Control
326
System Clock Operation Modes
327
System Clock Oscillator Controls
328
Oscillator Controls
328
DPLL Multiplier and Divider Factors
329
DPLL Power Modes
330
DPLL Power Mode Support
330
Mode)
331
DPLL Power Mode Control
331
LP Mode Control
331
Mode)
332
Clock Path Power-Down Control
332
DPLL Recalibration Controls
333
Common PRM Source-Clock Controls
335
Common PRM Source-Clock Gating Controls
335
Common CM Source-Clock Controls
337
Common Interface Clock Controls
338
Common CM Source-Clock Gating Controls
338
Common Interface Clock-Gating Controls
338
DPLL Power Domain Clock Controls
339
DPLL Power Domain Clock-Gating Controls
339
SGX Power Domain Clock Controls
340
SGX Power Domain Clock-Gating Controls
340
CORE Power Domain Clock Controls: Part
341
CORE Power Domain Clock Controls: Part
342
CORE Power Domain Clock-Gating Controls
342
EFUSE Power Domain Clock Controls
343
EFUSE Power Domain Clock-Gating Control
343
DSS Power Domain Clock Controls
344
DSS Power Domain Clock-Gating Controls
344
CAM Power Domain Clock Controls
345
USBHOST Power Domain Clock Controls
345
CAM Power Domain Clock-Gating Controls
345
USBHOST Power Domain Clock-Gating Controls
345
WKUP Power Domain Clock Controls
346
WKUP Power Domain Clock-Gating Controls
346
PER Power Domain Clock Controls: Part
347
PER Power Domain Clock Controls: Part
348
SMARTREFLEX Power Domain Clock Controls
349
PER Power Domain Clock-Gating Controls
349
SMARTREFLEX Power Domain Clock-Gating Controls
349
Processor Clock Configuration Controls
351
Processor Clock Configurations
351
Interface Clock Configuration Controls
352
Functional Clock Configuration Controls
352
Cm_Clksel1_Pll_Mpu
352
Power Domain Sleep/Wake-Up Transition
353
Device Power Reset and Clock Controllers
354
Power-State-Related Sleep Transition Actions
355
Mode)
356
MPU Power Domain Wake-Up Events
356
Pm_Evgenctrl_Mpu
356
NEON Power Domain Wake-Up Events
357
IVA2 Power Domain Wake-Up Events
357
SGX Power Domain Wake-Up Events
358
CORE Power Domain Wake-Up Events
358
DSS Power Domain Wake-Up Events
359
CAM Power Domain Wake-Up Events
359
USBHOST Power Domain Wake-Up Events
359
PER Power Domain Wake-Up Events
359
EMU Power Domain Wake-Up Events
360
WKUP Power Domain Wake-Up Events
360
Clock Domain Mute Conditions
361
Sleep Dependencies
363
Wake-Up Dependencies
364
Save-And-Restore Sequence
367
Interrupt Descriptions
369
MPU Interrupt Event Descriptions
369
Prm_Irqstatus_Iva2
369
Prm_Irqenable_Iva2
369
Overview
371
IVA2 Interrupt Event Descriptions
371
Overview of Device Voltage Domains
372
Overview of Device Voltage Distribution
374
Voltage Domain Controls Summary
375
VDD1 Voltage Domain Dependencies
376
VDD2 Voltage Domain Dependencies
376
Remaining Voltage Domain Dependencies
377
PRM Voltage Control Architecture
378
Smartreflex Integration
381
Smartreflex Module Functional Overview
382
Smartreflex Interrupts
384
Smartreflex Interrupt Enable and Status Bits
384
Voltage Processor Functional Overview
386
Voltage Processor Interrupts
386
Voltage Processor Interrupt Enable and Status Bits
387
Smartreflex - SMPS Communication for Automatic Voltage Adjustments
389
Device Off-Mode Control Overview
392
Cm_Revision
397
Cm_Sysconfig
397
Prm_Revision
397
Prm_Sysconfig
397
Prm_Irqstatus_Mpu
399
Prm_Irqenable_Mpu
399
Sys_Clkout2 Gating Polarity Control
401
Cm_Clkout_Ctrl
401
Cm_Polctrl
401
Prm_Clksel
402
Prm_Clkout_Ctrl
402
Prm_Sram_Pcharge
402
Prm_Clksrc_Ctrl
402
Cm_Clksel1_Pll_Iva2
403
Cm_Clksel2_Pll_Iva2
403
Cm_Clksel2_Pll_Mpu
403
Cm_Autoidle_Pll
403
Cm_Clksel1_Pll
403
Cm_Clksel2_Pll
403
Cm_Clksel3_Pll
403
Cm_Clksel4_Pll
403
Cm_Clken_Pll_Iva2
404
Cm_Clken_Pll_Mpu
404
Cm_Autoidle_Pll_Mpu
404
Cm_Clken_Pll
404
Cm_Clksel5_Pll
404
Cm_Autoidle_Pll_Iva2
405
Cm_Idlest_Ckgen
405
Cm_Idlest2_Ckgen
405
GFX Functional Clock Ratio Settings
406
Cm_Idlest_Pll_Iva2
406
Cm_Idlest_Pll_Mpu
406
Cm_Clksel_Core
406
Cm_Clksel_Sgx
406
Cm_Clksel_Wkup
406
Cm_Clksel_Dss
406
Cm_Clksel_Cam
406
Cm_Clksel_Per
406
Cm_Fclken_Iva2
407
Cm_Fclken1_Core
407
Cm_Iclken1_Core
407
Cm_Fclken_Sgx
407
Cm_Iclken_Sgx
407
Cm_Fclken_Wkup
407
Cm_Iclken_Wkup
407
Cm_Fclken_Dss
407
Cm_Iclken_Dss
407
Cm_Fclken_Cam
407
Interface Clock Autoidle Settings
408
Cm_Idlest_Iva2
408
Cm_Idlest_Mpu
408
Cm_Idlest1_Core
408
Cm_Idlest_Sgx
408
Cm_Idlest_Wkup
408
Cm_Autoidle_Wkup
408
Cm_Idlest_Dss
408
Cm_Autoidle_Dss
408
Cm_Idlest_Cam
408
Clock State Transition Settings
409
Cm_Clkstctrl_Iva2
409
Cm_Clkstctrl_Mpu
409
Cm_Clkstctrl_Core
409
Cm_Clkstctrl_Sgx
409
Cm_Clkstctrl_Dss
409
Cm_Clkstctrl_Cam
409
Cm_Clkstctrl_Per
409
Cm_Clkstctrl_Emu
409
Cm_Clkstctrl_Neon
409
Sleep Dependency Settings
410
Cm_Clkstst_Iva2
410
Cm_Clkstst_Mpu
410
Cm_Clkstst_Core
410
Cm_Sleepdep_Sgx
410
Cm_Clkstst_Sgx
410
Cm_Sleepdep_Dss
410
Cm_Clkstst_Dss
410
Cm_Sleepdep_Cam
410
Cm_Clkstst_Cam
410
Pm_Wken1_Core
411
Pm_Wken_Wkup
411
Pm_Wken_Dss
411
Pm_Wken_Per
411
Pm_Wken_Usbhost
411
Pm_Wkdep_Iva2
412
Pm_Wkst1_Core
412
Pm_Wkst_Wkup
412
Pm_Wkdep_Dss
412
Pm_Wkdep_Cam
412
Pm_Wkst_Per
412
Pm_Wkdep_Per
412
Pm_Wkst_Usbhost
412
Pm_Mpugrpsel1_Core
413
Pm_Iva2Grpsel1_Core
413
Pm_Wkdep_Sgx
413
Pm_Mpugrpsel_Wkup
413
Pm_Iva2Grpsel_Wkup
413
Pm_Mpugrpsel_Per
413
Pm_Iva2Grpsel_Per
413
Prm_Rsttime
413
Pm_Mpugrpsel_Usbhost
413
Pm_Iva2Grpsel_Usbhost
413
Rm_Rstctrl_Iva2
414
Prm_Rstctrl
414
Prm_Rstst
415
Pm_Pwstctrl_Iva2
416
Pm_Pwstctrl_Mpu
416
Pm_Pwstctrl_Core
416
Pm_Pwstctrl_Sgx
416
Pm_Pwstctrl_Dss
416
Pm_Pwstctrl_Cam
416
Pm_Pwstctrl_Per
416
Pm_Pwstctrl_Usbhost
416
Pm_Pwstst_Iva2
418
Pm_Pwstst_Mpu
418
Pm_Pwstst_Core
418
Pm_Pwstst_Sgx
418
Pm_Pwstst_Dss
418
Pm_Pwstst_Cam
418
Pm_Pwstst_Per
418
Pm_Pwstst_Emu
418
Pm_Pwstst_Usbhost
418
Pm_Prepwstst_Iva2
419
Pm_Prepwstst_Mpu
419
Pm_Prepwstst_Core
419
Pm_Prepwstst_Sgx
419
Pm_Prepwstst_Dss
419
Pm_Prepwstst_Cam
419
Pm_Prepwstst_Per
419
Pm_Prepwstst_Neon
419
Pm_Prepwstst_Usbhost
419
Off Mode Wakeup Using I
420
Prm_Voltctrl
421
Prm_Vc_Smps_Sa
422
Prm_Vc_Smps_Vol_Ra
422
Prm_Vc_Smps_Cmd_Ra
422
Prm_Vc_Ch_Conf
422
Prm_Vc_Bypass_Val
423
Functional Clock Basic Programming Model
425
Functional Clock Switching
426
Interface Clock Basic Programming Model
427
Domain Inactive STATE Basic Programming Model
428
Processor Clock Basic Programming Model
430
Wake-Up Basic Programming Model
432
Smartreflex Initialization Flow Chart
433
Voltage Processor Initialization Flow Chart
436
Voltage Controller Initialization Flow Chart
439
Smartreflex - OPP Change Flow Chart
442
Voltage Processor - OPP Change Flow Chart
445
Overview of Device/Twl5030 DVFS Management Architecture
447
VDD1 and VDD2 Voltage Domain Modules and Clock Sources
448
Smartreflex Voltage Control Registers in ID5 Register Group
449
Data Composition for Smartreflex Voltage Control Registers
449
Device/Twl5030 Smartreflex DVFS Overview Flow Chart
450
VDD1 and VDD2 Voltage Control through VMODE
456
Voltage Control through VMODE Flow Chart
458
CM Instance Summary
459
IVA2_CM Register Summary
459
Ocp_System_Reg_Cm Register Summary
466
MPU_CM Register Summary
467
CORE_CM Register Summary
473
SGX_CM Register Summary
488
WKUP_CM Register Summary
492
Clock_Control_Reg_Cm Register Summary
497
Register Call Summary for Register CM_CLKEN_PLL
500
DSS_CM Register Summary
510
CAM_CM Register Summary
518
PER_CM Register Summary
524
EMU_CM Register Summary
535
Global_Reg_Cm Register Summary
540
NEON_CM Register Summary
541
USBHOST_CM Register Summary
543
Register Call Summary for Register CM_AUTOIDLE_USBHOST
546
PRM Instance Summary
548
IVA2_PRM Register Summary
548
Rm_Rstst_Iva2
548
Ocp_System_Reg_Prm Register Summary
559
MPU_PRM Register Summary
568
Register Call Summary for Register PM_WKDEP_MPU
571
CORE_PRM Register Summary
576
Pm_Iva2Grpsel3_Core
576
Pm_Mpugrpsel3_Core
576
SGX_PRM Register Summary
591
WKUP_PRM Register Summary
596
Clock_Control_Reg_Prm Register Summary
600
DSS_PRM Register Summary
602
CAM_PRM Register Summary
607
PER_PRM Register Summary
611
EMU_PRM Register Summary
624
Global_Reg_Prm Register Summary
626
Prm_Vc_Cmd_Val_0
629
Register Call Summary for Register PRM_VC_CMD_VAL_0
629
Prm_Vc_Cmd_Val_1
630
Register Call Summary for Register PRM_VC_CMD_VAL_1
630
Prm_Vc_I2C_Cfg
631
Register Call Summary for Register PRM_VC_I2C_CFG
631
USBHOST_PRM Register Summary
654
SR Instance Summary
661
SR Register Summary
661
Register Call Summary for Register SRCONFIG
663
Register Call Summary for Register SRSTATUS
664
Register Call Summary for Register SENVAL
664
Register Call Summary for Register SENMIN
665
Register Call Summary for Register SENMAX
665
Register Call Summary for Register SENAVG
666
Register Call Summary for Register AVGWEIGHT
666
Register Call Summary for Register NVALUERECIPROCAL
667
Register Call Summary for Register IRQSTATUS
669
Register Call Summary for Register ERRCONFIG
672
MPU Subsystem Overview
676
MPU Subsystem Integration Overview
678
MPU Subsystem Clocking Scheme
679
MPU DPLL Clock Signals
680
MPU Subsystem Reset Scheme
681
MPU Subsystem Reset Signals
681
ARM Core Key Features
682
MPU Subsystem Clock Signal
683
ARM Reset Signals
683
Bridges Clock Signals
683
MPU Subsystem Reset Signal
683
Bridge Clock Signals
684
MPU Subsystem Reset Signal
684
MPU Subsystem Power Domain Overview
685
Overview of the MPU Subsystem Power Domain
686
MPU Power States
686
MPU DPLL Power Modes
686
MPU Retention Modes
687
MPU Subsystem Operation Power Modes
687
Power Mode Allowable Transitions
689
IVA2.2 Subsystem Highlight
694
IVA2.2 Subsystem Integration
696
IVA2.2 Internal Clock
697
IVA2.2 Subsystem Resets
698
IVA2.2 Power Domain
700
IVA2.2 EDMA Requests
701
IVA2.2 Subsystem EDMA Request Mappings
701
IVA2.2 Interrupt Management
703
IVA2.2 Interrupt Mappings
703
Tpcc_Er
704
IVA2.2 Subsystem Block Diagram
706
DSP Megamodule Block Diagram
707
DSP Megamodule INTC Block Diagram
711
Interrupt Selector Block Diagram
713
IVA2.2 EDMA Overview
717
TPCC Block Diagram
718
Tpcc_Qer
719
DMA/QDMA Channel Mapping and Param Entry
720
TPTC Block Diagram
723
Transfer Geometry
724
Tptcj_Pmpprxy
724
Tptcj_Sasrc
724
Tptcj_Dfbidxi
724
IVA2.2 EDMA Hardware Parameters
725
Tptcj_Dfopti
725
EDMA Memory Mapping for the Video Accelerator/Sequencer
726
IVA2.2 MMU Block Diagram
728
IVA2.2 MMU Translation Table Hierarchy
729
Video Accelerator/Sequencer Memory Mapping
730
SL2 Memory Interface Block Diagram
732
IVA2.2 WUGEN Description
734
Wugen_Pendevt2
734
WUGEN Event Generation
735
WUGEN Event Masking
736
WUGEN Event Mask Clear
737
SYSC Block Diagram
738
LSYS Input Interrupts
740
IVA2.2 Local Memories Hierarchy
741
IVA2.2 DSP Megamodule Cache Controller Features
741
IVA2 Boot Mode Configuration
744
Boot Loader Configuration
744
PDCCMD Programmed Value in IDLE Boot Mode
745
Header Format Used in Defautl Config Cache Mode
745
Header Format Used in User Defined Bootstrap Mode
746
IVA2 Boot Basic Programming Model
748
Cache Size Specified by L1PMODE
749
Cache Size Specified by L1DMODE
750
Cache Size Specified by L2MODE
750
Switching Cache Modes
750
Default Cache Configuration
751
Cache Mode Configuration
751
Sysc_Licfg0
755
Idma1_Count
758
Sysc_Licfg1
761
Idma0_Mask
763
Idma0_Source
763
Idma0_Dest
763
Idma0_Count
763
Ilf_Commandreg
772
Ime/Ilf Typical Use Flow Chart
773
Ivlcd Typical Use Flow Hart
774
Ivlcd_Sysstatus
774
Vlcd_Mpeg_Cbp
777
Ivlcd List of Register Values for Standard Algorithms
779
Cavlc_Bitptr
780
IVA2.2 Interrupt Flow
781
Wugen_Mevt0
783
Wugen_Mevt1
783
Process of Identifying Source Event of an Interrupt
787
L1P Memory Protection Registers
788
L1D Memory Protection Registers
789
L2 Memory Protection Registers
789
IVA2.2 Megamodule Memory Protection
790
Request-Type Access Controls
792
Tpcc_Mppag
792
IVA2 Power off
798
IVA2 Power down
799
IVA2 Wake up
800
Tpcc_Eeval
803
Instance Summary
804
IC Register Summary
805
Register Call Summary for Register Evtflagi
805
Register Call Summary for Register Evtseti
806
Register Call Summary for Register Evtclri
806
Register Call Summary for Register Evtmaski
807
Register Call Summary for Register Mevtflagi
807
Register Call Summary for Register Expmaski
808
Register Call Summary for Register Mexpflagi
808
Register Call Summary for Register Intmuxj
809
Register Call Summary for Register INTXSTAT
810
Register Call Summary for Register INTXCLR
810
Register Call Summary for Register INTDMASK
811
Register Call Summary for Register EVTASRT
812
SYS Register Summary
813
Register Call Summary for Register PDCCMD
814
Register Call Summary for Register REVID
815
IDMA Register Summary
816
Register Call Summary for Register CPUARBE
823
Register Call Summary for Register IDMAARBE
824
Register Call Summary for Register SDMAARBE
824
Register Call Summary for Register MDMAARBE
825
Register Call Summary for Register ICFGMPFAR
825
Register Call Summary for Register ICFGMPFSR
826
Register Call Summary for Register ICFGMPFCR
826
Register Call Summary for Register IBUSERR
827
Register Call Summary for Register IBUSERRCLR
827
XMC Register Summary
828
Register Call Summary for Register L2CFG
830
Register Call Summary for Register L1PCFG
830
Register Call Summary for Register L1PCC
831
Register Call Summary for Register L1DCFG
831
Register Call Summary for Register L1DCC
832
Register Call Summary for Register CPUARBU
833
Register Call Summary for Register IDMAARBU
833
Register Call Summary for Register SDMAARBU
834
Register Call Summary for Register UCARBU
834
Register Call Summary for Register CPUARBD
835
Register Call Summary for Register IDMAARBD
835
Register Call Summary for Register SDMAARBD
836
Register Call Summary for Register UCARBD
837
Register Call Summary for Register L2WBAR
837
Register Call Summary for Register L2WWC
837
Register Call Summary for Register L2WIBAR
838
Register Call Summary for Register L2WIWC
838
Register Call Summary for Register L2IBAR
839
Register Call Summary for Register L2IWC
839
Register Call Summary for Register L1PIBAR
839
Register Call Summary for Register L1PIWC
840
Register Call Summary for Register L1DWIBAR
840
Register Call Summary for Register L1DWIWC
841
Register Call Summary for Register L1DWBAR
841
Register Call Summary for Register L1DWWC
841
Register Call Summary for Register L1DIBAR
842
Register Call Summary for Register L1DIWC
842
Register Call Summary for Register L2WB
843
Register Call Summary for Register L2WBINV
843
Register Call Summary for Register L2INV
844
Register Call Summary for Register L1PINV
844
Register Call Summary for Register L1DWB
845
Register Call Summary for Register L1DWBINV
845
Register Call Summary for Register L1DINV
846
Register Call Summary for Register Mari
846
Register Call Summary for Register L2MPFAR
847
Register Call Summary for Register L2MPFSR
847
Register Call Summary for Register L2MPFCR
848
Register Call Summary for Register L2Mppaj
849
Register Call Summary for Register L1PMPFAR
849
Register Call Summary for Register L1PMPFSR
850
Register Call Summary for Register L1PMPFCR
850
Register Call Summary for Register L1Pmppak
851
Register Call Summary for Register L1DMPFAR
852
Tpcc_Qwmthra
855
Tpcc_Qwmthrb
855
Tpcc_Ccstat
855
Tpcc_Mpfar
855
Tpcc_Mpfsr
855
Tpcc_Mpfcr
855
Tpcc_Ecr
855
Tpcc_Esr
855
Tpcc_Esrh
855
Tpcc_Cer
855
Tpcc_Qeecr
856
Tpcc_Qeesr
856
Tpcc_Qser
856
Tpcc_Qsecr
856
Register Call Summary for Register TPCC_ESR
897
Tptcj_Errcmd
955
Tptcj_Rdrate
955
Tptcj_Popt
955
Tptcj_Psrc
955
Tptcj_Pcnt
955
Tptcj_Pdst
955
Tptcj_Pbidx
955
Tptcj_Saopt
955
Tptcj_Sacnt
955
Tptcj_Sadst
955
SYSC Register Summary
979
WUGEN Register Summary
985
Wugen_Revision
985
Wugen_Sysconfig
985
Wugen_Pendevtclr0
985
Wugen_Pendevtclr1
985
Wugen_Pendevtclr2
985
Wugen_Mevtclr0
990
Register Call Summary for Register WUGEN_MEVTCLR0
991
Wugen_Mevtclr1
991
Wugen_Mevt2
992
Register Call Summary for Register WUGEN_MEVTCLR1
992
Wugen_Mevtclr2
992
Register Call Summary for Register WUGEN_MEVTCLR2
993
Wugen_Mevtset0
994
Register Call Summary for Register WUGEN_MEVTSET0
995
Wugen_Mevtset1
995
Register Call Summary for Register WUGEN_MEVTSET1
996
Wugen_Mevtset2
996
Register Call Summary for Register WUGEN_MEVTSET2
997
Wugen_Pendevt0
1001
Wugen_Pendevt1
1002
Ivlcd Register Mapping Summary
1004
Ivlcd_Sysconfig
1004
Ivlcd_Cpustatusreg
1004
Ivlcd_Configreg
1004
Ivlcd_Command
1004
Vlcd_Start
1004
Vlcd_Mode
1004
Vlcd_Qin_Addr
1004
Vlcd_Qout_Addr
1004
Vlcd_Iqin_Addr
1004
Vlcd_Bits_Bptr
1005
Vlcd_Bits_Word
1005
Vlcd_Byte_Align
1005
Vlcd_Head_Addr
1005
Vlcd_Head_Num
1005
Vlcd_Vld_Errctl
1005
Vlcd_Vld_Errstat
1005
Vlcd_Ring_Start
1005
Vlcd_Ring_End
1005
Vlcd_Ctrl
1005
Ivlcd_Revision
1006
Vlcd_Mpeg_Q
1016
Register Call Summary for Register VLCD_MPEG_Q
1016
Vlcd_Mpeg_Delta_Q
1016
Register Call Summary for Register VLCD_MPEG_DELTA_Q
1016
Vlcd_H264_Mode
1034
Register Call Summary for Register VLCD_H264_MODE
1035
Ime_Cpustatusreg
1057
Ime_Irqlog
1057
Ime_Latesterrors
1057
Ime_Configreg
1057
Ime_Commandreg
1057
Ime_Programbufferlinenmsbi
1060
Register Call Summary for Register Ime_Programbufferlinenmsbi
1060
Ime_Referenceblockk
1060
Register Call Summary for Register Ime_Referenceblockk
1061
Ime_Coeffregbankl
1061
Register Call Summary for Register Ime_Coeffregbankl
1061
Ime_Parameterstacklj
1061
Register Call Summary for Register Ime_Parameterstacklj
1061
Ime_Parameterstackhj
1062
Register Call Summary for Register Ime_Parameterstackhj
1062
Ime_Minerrorthreshold
1063
Register Call Summary for Register Ime_Minerrorthreshold
1063
Ime_Absminreached
1063
Register Call Summary for Register Ime_Absminreached
1063
Ime_Sl2Instaddress
1066
Register Call Summary for Register Ime_Sl2Instaddress
1066
Ilf Register Mapping Summary
1068
Ilf_Sysconfig
1068
Ilf_Sysstatus
1068
Ilf_Cpustatusreg
1068
Ilf_Irqlog
1068
Ilf_Efptd
1068
Ilf_Configreg
1068
Ilf_Instbuffer_Address
1068
Ilf_Revision
1069
Ilf_Programbufferlinenlsbi
1070
Register Call Summary for Register Ilf_Programbufferlinenlsbi
1070
Ilf_Programbufferlinenmsbi
1071
Register Call Summary for Register Ilf_Programbufferlinenmsbi
1071
Ilf_Parameterstackupj
1071
Register Call Summary for Register Ilf_Parameterstackupj
1071
Ilf_Parameterstacklwk
1071
Register Call Summary for Register Ilf_Parameterstacklwk
1072
Ilf_Efptableentryl
1072
Register Call Summary for Register Ilf_Efptableentryl
1072
Ilf_Parseddatareg0
1075
Register Call Summary for Register Ilf_Parseddatareg0
1075
Ilf_Parseddatareg1
1076
Register Call Summary for Register Ilf_Parseddatareg1
1076
Ilf_Parseddatareg2
1076
Register Call Summary for Register Ilf_Parseddatareg2
1077
Ilf_Linesfilterprototypes
1077
Register Call Summary for Register Ilf_Linesfilterprototypes
1077
Ilf_Cliplimitsentryn
1078
Register Call Summary for Register Ilf_Cliplimitsentryn
1078
IA_GEM Register Mapping Summary
1079
IA_EDMA Register Mapping Summary
1080
IA_SEQ Register Mapping Summary
1081
Camera ISP Overview Diagram
1087
Camera ISP Functions
1091
IO Description
1092
Camera ISP Connectivity Schemes
1093
Camera ISP Synchronization Signals and Frame Timing in SYNC Mode
1096
Camera ISP Synchronization Signals and Data Timing in SYNC Mode
1096
Camera ISP SYNC Mode Clock Gating
1097
Camera ISP JPEG Stream Timing Diagrams
1097
Camera ISP Data Timing with Embedded Synchronization Signals (8-Bit Case)
1098
Camera ISP Video Timing Reference Codes for SAV and EAV
1098
Camera ISP F, V, H Signal Descriptions
1098
Camera ISP F, V, H Protection (Error-Correction) Bits
1099
Camera ISP BT.656 Mode Data Format in SDRAM
1099
Camera ISP CSI1/CCP2B Image Data Operating Modes and Alignment Constraints
1100
Camera ISP Example of 0Xff00 0002 Transmission
1101
Camera ISP CSI1/CCP2B Image Data Operating Modes and Alignment Constraints
1101
Camera ISP CSI1/CCP2 YUV422 Big Endian
1102
Camera ISP CSI1/CCP2 YUV422 Little Endian
1103
Camera ISP CSI1/CCP2 YUV420
1104
Camera ISP CSI1/CCP2 RGB888
1105
Camera ISP CSI1/CCP2 RGB565
1106
Camera ISP CSI1/CCP2 RGB444
1106
Camera ISP CSI1/CCP2 RAW 6
1106
Camera ISP CSI1/CCP2 RAW 7
1107
Camera ISP CSI1/CCP2 RAW8
1109
Camera ISP CSI1/CCP2 RAW10
1110
Camera ISP CSI1/CCP2 RAW12
1111
Camera ISP CSI1/CCP2 JPEG8 and JPEG8 FSP
1112
Camera ISP CSI2 Two Data-Lane Merger Configuration
1113
Camera ISP CSI2 One Data-Lane Configuration
1113
Camera ISP CSI2 Protocol Layer with Short and Long Packets
1114
Camera ISP CSI2 Short Packet Structure
1114
Camera ISP CSI2 Long Packet Structure
1115
Camera ISP CSI2 Long Packet Structure Description
1115
Camera ISP CSI2 Data Identifier Structure
1116
Camera ISP CSI2 Virtual Channel
1116
Camera ISP CSI2 Pixel Format Modes
1116
Camera ISP CSI2 Synchronization Codes
1117
Camera ISP CSI2 General Frame Structure (Informative)
1119
Camera ISP CSI2 Digital Interlaced Video Frame (Informative)
1120
Camera ISP CSI2 YUV420 8-Bit
1121
Camera ISP CSI2 YUV420 10-Bit
1122
Camera ISP CSI2 YUV420 8-Bit Legacy
1123
Camera ISP CSI2 YUV420 8-Bit + CSPS
1124
Camera ISP CSI2 YUV420 10-Bit + CSPS
1125
Camera ISP CSI2 YUV422 8-Bit
1126
Camera ISP CSI2 YUV422 10-Bit
1126
Camera ISP CSI2 RGB565
1127
Camera ISP CSI2 RGB888
1128
Camera ISP CSI2 RGB666
1129
Camera ISP CSI2 RGB444
1130
Camera ISP CSI2 RGB555
1130
Camera ISP CSI2 RAW6
1131
Camera ISP CSI2 RAW7
1132
Camera ISP CSI2 RAW8
1133
Camera ISP CSI2 RAW10
1134
Camera ISP CSI2 RAW12
1135
Camera ISP CSI2 RAW14
1136
Camera ISP CSI2 JPEG8
1137
Camera ISP CSI2 Generic
1137
Camera ISP CSI2 Byte-Swap
1138
Camera ISP Integration
1139
Camera ISP Clock Tree Diagram
1140
Camera ISP Clock Descriptions
1140
Camera ISP Cam_Xclka Configuration
1141
Camera ISP Cam_Xclkb Configuration
1142
Ccp2_Sysconfig
1142
Isp_Sysconfig
1144
Camera ISP Interrupt Generation Tree
1145
Camera ISP Interrupts
1145
Camera ISP CBUFF Interrupt Details
1147
Cbuff_Irqenable
1147
Camera ISP CSI1/CCP2B Receiver Interrupt Details
1148
Camera ISP CSI2A and CSI2C Receivers Event Generation
1151
Ccp2_Lcm_Irqenable
1151
Ccp2_Lcm_Irqstatus
1151
Camera ISP CSI2A and CSI2C Receiver Event Generation from PHY
1152
Camera ISP CSI2A and CSI2C Ctx Receiver Event Generation
1153
Camera ISP Block Diagram
1155
Camera ISP Allowed Data Flows for Hardware
1156
Camera Isp/Data Path/Raw RGB Images
1157
Camera ISP / Data Path/Yuv4:2:2 Images
1158
Camera Isp/Data Path/Jpeg Images
1159
Camera ISP CSI1/CCP2B Receiver Block Diagram
1160
Camera ISP CSI1/CCP2B Transmitter Classification
1160
Ccp2_Lcx_Ctrl
1161
Camera ISP CSI1/CCP2B Synchronization State-Machine
1162
Camera ISP CSI1/CCP2B Frame Structure: Non-JPEG Data Format
1163
Camera ISP CSI1/CCP2B Frame Structure: JPEG8 Data Format
1163
Camera ISP CSI1/CCP2B Data Structure
1164
Camera ISP CSI1/CCP2B Muxing
1165
Camera ISP CSI1/CCP2B Logical Channel Values in Synchronization Codes
1165
Camera ISP CSI1/CCP2B Memory-To-Memory Supported Operations
1166
Camera ISP CSI1/CCP2B Memory-To-Video Processing Hardware Supported Formats
1168
Camera ISP CSI1/CCP2B Data Organization in Memory
1170
Ccp2_Lcm_Src_Addr
1170
Camera ISP CSI1/CCP2B Data Organization in Memory Continued
1171
Camera ISP CSI1/CCP2B Data Organization in Memory
1172
Camera ISP CSI1/CCP2B Data Packing Benefit and Constraints
1172
Ccp2_Lcm_Src_Ofst
1172
Camera ISP CSI1/CCP2B Output Width Restrictions in Memory-To-Memory Operation
1173
Ccp2_Lcm_Prefetch
1173
Camera ISP CSI2 Receiver Block Diagram
1176
Camera ISP CSI2 ECC Event Logging
1177
Camera ISP CSI2 RAW Image Transcoding Diagram
1179
Camera ISP Pixel Format Modes
1179
Camera ISP CSI2 Frame Cropping
1180
Camera ISP CSI2 Transcode Alignment Constraints
1181
Camera ISP CSI2 Supported Transcoding Output Formats
1181
Camera ISP CSI2 SHORT_PACKET Field Format
1182
Csi2_Irqstatus
1182
Camera ISP CSI2 Virtual Channel to Context
1183
Csi2_Ctrl
1183
Camera ISP CSI2 Pixel Data Destination Setting in Progressive and Interlaced Mode
1185
Camera ISP CSI2 PHY Overview
1185
Camera ISP CSIPHY Power FSM
1186
Camera ISP CSI2 Possible Time-Out Value for Rxmode Counter
1186
Csi2_Complexio_Cfg1
1186
Csi2_Timing
1186
Camera ISP CSI2 Rxmode and Stopstate FSM
1187
Camera ISP Timing Control Block Diagram
1188
Camera ISP Timing Control Control-Signal Generation
1189
Camera ISP Timing Control Control-Signal Generator: CNTCLK Frequencies
1190
Camera ISP Timing Control Use of Cam_Global_Reset with Global Reset Release Camera Modules
1191
Camera ISP Bridge-Lane Shifter
1192
Camera ISP CCDC Block Diagram
1194
Isp_Ctrl
1195
Camera ISP CCDC Optical Clamp Representation
1196
Ccdc_Clamp
1196
Ccdc_Colptn
1196
Ccdc_Hd_Vd_Wid
1197
Ccdc_Pix_Lines
1197
Ccdc_Vert_Lines
1197
Ccdc_Fmtcfg
1197
Camera ISP CCDC Data Formatter Conversion Area Selection
1198
Camera ISP CCDC Reformatter Output Limitations
1198
Ccdc_Culling
1200
Camera ISP CCDC/Culling: Example for Decimation Pattern
1201
Ccdc_Alaw
1201
Camera ISP CCDC A-Law Table
1202
Camera ISP CCDC CCDC_SDOFST Description
1202
Ccdc_Syn_Mode
1202
Ccdc_Hsize_Off
1202
Ccdc_Sdofst
1202
Ccdc_Sdr_Addr
1202
Camera ISP CCDC/Line-Output Control: Sample Formats of Input and Output Images
1203
Camera ISP CCDC Memory Output Format for RAW Data
1204
Camera ISP CCDC Memory Output Format for YUV Data
1205
Camera ISP VPBE Preview Engine Block Diagram
1207
Prv_Horz_Info
1207
Prv_Vert_Info
1207
Prv_Dsdr_Addr
1207
Camera ISP VPBE Preview Horizontal Distances for Different Patterns
1208
Prv_Wadd_Offset
1208
Prv_Pcr
1210
Prv_Blkadjoff
1210
Prv_Rgb_Off1
1210
Prv_Csc_Offset
1211
Camera ISP VPBE Preview Image Cropping by Preview Functions
1212
Prv_Setup_Yc
1212
Camera ISP VPBE Resizer Use Constraints
1213
Camera ISP VPBE Resizer Process
1214
Rsz_Sdr_Inadd
1214
Rsz_Sdr_Inoff
1214
Camera ISP VPBE Resizer Resizer in Memory-Input Mode
1215
Rsz_Cnt
1215
Rsz_In_Start
1215
Camera ISP VPBE Resizer Typical Sample-Rate Converter
1216
Camera ISP VPBE Resizer Functionality
1216
Camera ISP VPBE Resizer Approximation Scheme
1216
Camera ISP VPBE Resizer Cutoff Frequency for Low-Pass Filter
1216
Rsz_Hfilt10
1216
Camera ISP VPBE Resizer Arrangement of the Filter Coefficients
1217
Rsz_Hfilt3130
1217
Camera ISP VPBE Resizer Alignment of Input Pixels to Tap Coefficients
1218
Camera ISP VPBE Resizer Input Size Calculations
1218
Rsz_Yenh
1218
Camera ISP VPBE Resizer Pseudo-Code Description of the Resizer Algorithm in the 4-Tap/8-Phase Mode
1219
Camera ISP VPBE Resizer Pseudo-Code Description of the Resizer Algorithm in the 7-Tap/4-Phase Mode
1220
Camera ISP VPBE Resizer Processing Example for 1:2:56 Horizontal Resize
1223
Camera ISP Histogram Process
1226
Camera ISP Histogram White Balance Field-To-Pattern Assignments
1226
Hist_Cnt
1226
Hist_Wb_Gain
1226
Hist_H_V_Info
1226
Camera ISP Histogram Color Pattern Index
1227
Camera ISP Histogram Regions and Bins
1227
Hist_Rn_Vert
1227
Camera ISP Histogram Region Priority
1228
Camera ISP Shared Buffer Logic Block Diagram
1230
Camera ISP Shared Buffer Logic Fixed Parameters
1231
Camera ISP Shared Buffer Logic Number of Request Registers
1233
Camera ISP Circular Buffer Single Slice Buffer Example (Write Mode)
1235
Camera ISP Circular Buffer Control Feedback Loop Example
1237
Cbuffx_Ctrl
1237
Camera ISP Circular Buffer Extended Slice Buffer Example
1238
Camera ISP Circular Buffer Fragmentation Support
1238
Cbuffx_Addry
1238
Camera ISP Circular Buffer Fragmentation Support Physical Window Addresses
1239
Camera ISP Circular Buffer VRFB Maximum Supported Frame Size
1239
Camera ISP Circular Buffer VRFB Extended Supported Frame Size
1239
Camera ISP Circular VRFB Buffer Performed Translation
1240
Camera ISP Circular Buffer Internal Variables
1240
Camera ISP Circular Buffer Internal State after Reset
1240
Cbuff_Irqstatus
1240
Cbuff_Vrfb_Ctrl
1240
Camera ISP Circular Buffer Address Identification
1241
Cbuffx_Start
1241
Cbuffx_End
1241
Camera ISP Circular Buffer Address Translation
1242
Camera ISP Circular Buffer Window Level Increment
1242
Camera ISP Circular Buffer Window Level Comparison
1242
Cbuffx_Windowsize
1243
Camera ISP PRCM Registers Settings
1244
Ccp2_Dbg
1249
Ccp2_Lcx_Dat_Start
1250
Ccp2_Lcx_Dat_Ping_Addr
1251
Camera ISP CSI1/CCP2B SOF and EOF Region Settings
1252
Ccp2_Lcx_Code
1252
Ccp2_Lcx_Stat_Start
1252
Ccp2_Lcx_Stat_Size
1252
Camera ISP CSI1/CCP2B Pixel Data Region Settings
1253
Camera ISP CSI1/CCP2B Pixel Data Destination Settings
1255
Ccp2_Ctrl
1256
Camera ISP CSI2 Receiver Global Reset Flow Chart
1257
Csi2_Sysconfig
1257
Camera ISP CSI2 Receiver-Supported Data Types
1259
Tctrl_Ctrl
1262
Tctrl_Frame
1262
Cam_Strobe Signal-Generation for Red-Eye Removal
1264
Tctrl_Pstrb_Delay
1264
Tctrl_Strb_Delay
1264
Tctrl_Pstrb_Length
1264
Tctrl_Strb_Length
1264
Camera ISP CCDC Required Configuration Parameters
1265
Camera ISP CCDC Conditional Configuration Parameters
1265
Ccdc_Lsc_Config
1265
Ccdc_Fmt_Vert
1266
Camera ISP CCDC Dependencies Among Framing Settings in Data Flow
1267
Isp_Irq0Enable
1268
Isp_Irq1Enable
1268
Ccdc_Vdint
1268
Camera ISP CCDC CCDC_VD0_IRQ/CCDC_VD1_IRQ Interrupt Behavior When VDPOL
1269
Camera ISP CCDC CCDC_VD2_IRQ Interrupt Behavior
1269
Ccdc_Pcr
1269
Ccdc_Vert_Start
1270
Ccdc_Rec656If
1271
Camera ISP CCDC HS/VS Sync Pulse Output Timings
1272
Camera ISP CCDC Mosaic Filter - CCDC_COLPTN Bit Field Settings
1273
Ccdc_Dcsub
1273
Camera ISP CCDC Conventional Readout Pattern 1 to
1274
Ccdc_Fpc
1274
Ccdc_Prgeven1
1274
Camera ISP CCDC Dual Readout Pattern 1 to
1275
Ccdc_Prgeven0
1275
Ccdc_Prgodd0
1275
Camera ISP CCDC Dual Readout Pattern 1 to
1276
Camera ISP CCDC CCDC_ALAW [2:0] GWDI
1277
Camera ISP CCDC Data Packing - Pixel Ordering
1278
Camera ISP CCDC Clipping Window before Output to Memory
1279
Ccdc_Horz_Info
1279
Ccdc_Cfg
1279
Camera ISP Preview Engine Required Configuration Parameters
1281
Camera ISP Preview Engine Conditional Configuration Parameters
1281
Prv_Rgb_Mat1
1281
Prv_Csc0
1281
Prv_Nf
1282
Prv_Cdc_Thrx
1282
Isp_Irq1Status
1283
Prv_Ave
1284
Camera ISP Resizer Required Configuration Parameters
1285
Camera ISP Resizer Conditional Configuration Parameters
1285
Camera ISP Resizer Firmware Interactions for Memory-Input Resizing
1286
Isp_Irq0Status
1286
Rsz_Pcr
1286
Rsz_Out_Size
1288
Rsz_In_Size
1288
Camera ISP Resizer How to Set Input Height and Width
1289
Camera ISP H3A AF Engine Required Configuration Parameters
1290
Camera ISP H3A AF Engine Conditional Configuration Parameters
1290
Camera ISP H3A AEW Engine Required Configuration Parameters
1290
Camera ISP Histogram Required Configuration Parameters
1293
Camera ISP Histogram Conditional Configuration Parameters
1293
Hist_Rn_Horz
1293
Hist_Pcr
1294
Camera ISP Central-Resource SBL Write-Buffer Overflow Events
1295
Camera ISP Central-Resource SBL Read-Buffer Underflow Events
1296
Camera ISP Central-Resource SBL Video-Port Interface Bandwidth Balancing
1297
Camera ISP Central-Resource SBL Memory Read Bandwidth Balancing
1298
Sbl_Sdr_Req_Exp
1298
Cbuffx_Threshold
1299
Camera ISP Software Reset Sequence
1301
Camera ISP Software Register Settings
1301
Camera ISP Instance Summary
1302
ISP Register Mapping Summary
1302
Isp_Revision
1302
Isp_Sysstatus
1302
Tctrl_Greset_Length
1302
Tctrl_Pstrb_Replay
1302
Tctrl_Shut_Delay
1302
ISP_CBUFF Register Summary
1329
Register Call Summary for Register Cbuffx_Ctrl
1335
ISP_CCP2 Register Summary
1340
Ccp2_Revision
1340
Ccp2_Sysstatus
1340
Ccp2_Ctrl1
1340
Ccp2_Lcx_Sof_Addr
1340
Ccp2_Lcx_Eof_Addr
1340
Ccp2_Lcx_Dat_Size
1340
Ccp2_Lcx_Dat_Pong_Addr
1340
Ccp2_Lcx_Dat_Ofst
1340
Ccp2_Lcm_Ctrl
1340
Ccp2_Lc01_Irqenable
1343
Register Call Summary for Register CCP2_LC01_IRQENABLE
1345
Ccp2_Lc01_Irqstatus
1345
Register Call Summary for Register CCP2_LC01_IRQSTATUS
1347
Ccp2_Lc23_Irqenable
1348
Register Call Summary for Register CCP2_LC23_IRQENABLE
1350
Ccp2_Lc23_Irqstatus
1350
Register Call Summary for Register CCP2_LC23_IRQSTATUS
1352
Ccp2_Gnq
1355
Register Call Summary for Register Ccp2_Lcx_Ctrl
1361
Register Call Summary for Register Ccp2_Lcx_Stat_Size
1363
Register Call Summary for Register Ccp2_Lcx_Dat_Pong_Addr
1366
ISP_CCDC Register Summary
1372
Ccdc_Fmt_Addr_I
1396
Register Call Summary for Register Ccdc_Fmt_Addr_I
1397
ISP_HIST Register Summary
1404
ISP_H3A Register Summary
1411
H3A_Pid
1412
Register Call Summary for Register H3A_PID
1412
H3A_Pcr
1412
Register Call Summary for Register H3A_PCR
1413
H3A_Afpax1
1413
Register Call Summary for Register H3A_AFPAX1
1414
H3A_Afpax2
1414
Register Call Summary for Register H3A_AFPAX2
1414
H3A_Afpaxstart
1415
Register Call Summary for Register H3A_AFPAXSTART
1415
H3A_Afiirsh
1415
Register Call Summary for Register H3A_AFIIRSH
1415
H3A_Afbufst
1416
Register Call Summary for Register H3A_AFBUFST
1416
H3A_Afcoef010
1416
Register Call Summary for Register H3A_AFCOEF010
1417
H3A_Afcoef032
1417
Register Call Summary for Register H3A_AFCOEF032
1417
H3A_Afcoef054
1417
Register Call Summary for Register H3A_AFCOEF054
1418
H3A_Afcoef076
1418
Register Call Summary for Register H3A_AFCOEF076
1418
H3A_Afcoef098
1418
Register Call Summary for Register H3A_AFCOEF098
1419
H3A_Afcoef0010
1419
Register Call Summary for Register H3A_AFCOEF0010
1419
H3A_Afcoef110
1419
Register Call Summary for Register H3A_AFCOEF110
1419
H3A_Afcoef132
1420
Register Call Summary for Register H3A_AFCOEF132
1420
H3A_Afcoef154
1420
Register Call Summary for Register H3A_AFCOEF154
1420
H3A_Afcoef176
1421
Register Call Summary for Register H3A_AFCOEF176
1421
H3A_Afcoef198
1421
Register Call Summary for Register H3A_AFCOEF198
1421
H3A_Afcoef1010
1422
Register Call Summary for Register H3A_AFCOEF1010
1422
H3A_Aewwin1
1422
Register Call Summary for Register H3A_AEWWIN1
1423
H3A_Aewinstart
1423
Register Call Summary for Register H3A_AEWINSTART
1423
H3A_Aewinblk
1424
Register Call Summary for Register H3A_AEWINBLK
1424
H3A_Aewsubwin
1424
Register Call Summary for Register H3A_AEWSUBWIN
1425
H3A_Aewbufst
1425
Register Call Summary for Register H3A_AEWBUFST
1425
ISP_PREVIEW Register Summary
1425
Prv_Hmed
1426
Prv_Wb_Dgain
1426
Prv_Wbgain
1426
Prv_Wbsel
1426
Prv_Cfa
1426
Prv_Rgb_Mat2
1426
Prv_Rgb_Mat3
1426
Prv_Rgb_Mat4
1426
Prv_Rgb_Mat5
1426
Prv_Rgb_Off2
1426
Register Call Summary for Register PRV_NF
1437
Register Call Summary for Register PRV_RGB_MAT1
1442
Register Call Summary for Register PRV_RGB_MAT5
1444
Register Call Summary for Register PRV_RGB_OFF2
1445
ISP_RESIZER Register Summary
1450
Rsz_Sdr_Outadd
1451
Rsz_Sdr_Outoff
1451
Rsz_Hfilt32
1451
Rsz_Hfilt54
1451
Rsz_Hfilt76
1451
Rsz_Hfilt98
1451
Rsz_Hfilt1110
1451
Rsz_Hfilt1312
1451
Rsz_Hfilt1514
1451
Rsz_Hfilt1716
1451
ISP_SBL Register Mapping Summary
1475
Sbl_Pcr
1475
Sbl_Glb_Reg_0
1479
Register Call Summary for Register SBL_GLB_REG_0
1480
Sbl_Glb_Reg_1
1480
Register Call Summary for Register SBL_GLB_REG_1
1481
Sbl_Glb_Reg_2
1481
Register Call Summary for Register SBL_GLB_REG_2
1482
Sbl_Glb_Reg_3
1482
Register Call Summary for Register SBL_GLB_REG_3
1483
Sbl_Glb_Reg_4
1483
Register Call Summary for Register SBL_GLB_REG_4
1484
Sbl_Glb_Reg_5
1484
Register Call Summary for Register SBL_GLB_REG_5
1485
Sbl_Glb_Reg_6
1485
Register Call Summary for Register SBL_GLB_REG_6
1486
Sbl_Glb_Reg_7
1486
Register Call Summary for Register SBL_GLB_REG_7
1487
Sbl_Ccdc_Wr_0
1487
Register Call Summary for Register SBL_CCDC_WR_0
1488
Sbl_Ccdc_Wr_1
1488
Register Call Summary for Register SBL_CCDC_WR_1
1488
Sbl_Ccdc_Wr_2
1489
Register Call Summary for Register SBL_CCDC_WR_2
1489
Sbl_Ccdc_Wr_3
1489
Register Call Summary for Register SBL_CCDC_WR_3
1490
Sbl_Ccdc_Fp_Rd_0
1490
Register Call Summary for Register SBL_CCDC_FP_RD_0
1490
Sbl_Ccdc_Fp_Rd_1
1491
Register Call Summary for Register SBL_CCDC_FP_RD_1
1491
Sbl_Prv_Rd_0
1491
Register Call Summary for Register SBL_PRV_RD_0
1492
Sbl_Prv_Rd_1
1492
Register Call Summary for Register SBL_PRV_RD_1
1492
Sbl_Prv_Rd_2
1493
Register Call Summary for Register SBL_PRV_RD_2
1493
Sbl_Prv_Rd_3
1493
Register Call Summary for Register SBL_PRV_RD_3
1494
Sbl_Prv_Wr_0
1494
Register Call Summary for Register SBL_PRV_WR_0
1494
Sbl_Prv_Wr_1
1495
Register Call Summary for Register SBL_PRV_WR_1
1495
Sbl_Prv_Wr_2
1495
Register Call Summary for Register SBL_PRV_WR_2
1496
Sbl_Prv_Wr_3
1496
Register Call Summary for Register SBL_PRV_WR_3
1496
Sbl_Prv_Dk_Rd_0
1496
Register Call Summary for Register SBL_PRV_DK_RD_0
1497
Sbl_Prv_Dk_Rd_1
1497
Register Call Summary for Register SBL_PRV_DK_RD_1
1498
Sbl_Prv_Dk_Rd_2
1498
Register Call Summary for Register SBL_PRV_DK_RD_2
1498
Sbl_Prv_Dk_Rd_3
1498
Register Call Summary for Register SBL_PRV_DK_RD_3
1499
Sbl_Rsz_Rd_0
1499
Register Call Summary for Register SBL_RSZ_RD_0
1500
Sbl_Rsz_Rd_1
1500
Register Call Summary for Register SBL_RSZ_RD_1
1500
Sbl_Rsz_Rd_2
1500
Register Call Summary for Register SBL_RSZ_RD_2
1501
Sbl_Rsz_Rd_3
1501
Register Call Summary for Register SBL_RSZ_RD_3
1502
Sbl_Rsz1_Wr_0
1502
Register Call Summary for Register SBL_RSZ1_WR_0
1502
Sbl_Rsz1_Wr_1
1502
Register Call Summary for Register SBL_RSZ1_WR_1
1503
Sbl_Rsz1_Wr_2
1503
Register Call Summary for Register SBL_RSZ1_WR_2
1503
Sbl_Rsz1_Wr_3
1504
Register Call Summary for Register SBL_RSZ1_WR_3
1504
Sbl_Rsz2_Wr_0
1504
Register Call Summary for Register SBL_RSZ2_WR_0
1505
Sbl_Rsz2_Wr_1
1505
Register Call Summary for Register SBL_RSZ2_WR_1
1505
Sbl_Rsz2_Wr_2
1505
Register Call Summary for Register SBL_RSZ2_WR_2
1506
Sbl_Rsz2_Wr_3
1506
Register Call Summary for Register SBL_RSZ2_WR_3
1507
Sbl_Rsz3_Wr_0
1507
Register Call Summary for Register SBL_RSZ3_WR_0
1507
Sbl_Rsz3_Wr_1
1507
Register Call Summary for Register SBL_RSZ3_WR_1
1508
Sbl_Rsz3_Wr_2
1508
Register Call Summary for Register SBL_RSZ3_WR_2
1508
Sbl_Rsz3_Wr_3
1509
Register Call Summary for Register SBL_RSZ3_WR_3
1509
Sbl_Rsz4_Wr_0
1509
Register Call Summary for Register SBL_RSZ4_WR_0
1510
Sbl_Rsz4_Wr_1
1510
Register Call Summary for Register SBL_RSZ4_WR_1
1510
Sbl_Rsz4_Wr_2
1510
Register Call Summary for Register SBL_RSZ4_WR_2
1511
Sbl_Rsz4_Wr_3
1511
Register Call Summary for Register SBL_RSZ4_WR_3
1512
Sbl_Hist_Rd_0
1512
Register Call Summary for Register SBL_HIST_RD_0
1512
Sbl_Hist_Rd_1
1512
Register Call Summary for Register SBL_HIST_RD_1
1513
Sbl_H3A_Af_Wr_0
1513
Register Call Summary for Register SBL_H3A_AF_WR_0
1513
Sbl_H3A_Af_Wr_1
1514
Register Call Summary for Register SBL_H3A_AF_WR_1
1514
Sbl_H3A_Aeawb_Wr_0
1514
Register Call Summary for Register SBL_H3A_AEAWB_WR_0
1515
Sbl_H3A_Aeawb_Wr_1
1515
Register Call Summary for Register SBL_H3A_AEAWB_WR_1
1515
Sbl_Csia_Wr_0
1515
Register Call Summary for Register SBL_CSIA_WR_0
1516
Sbl_Csia_Wr_1
1516
Register Call Summary for Register SBL_CSIA_WR_1
1517
Sbl_Csia_Wr_2
1517
Register Call Summary for Register SBL_CSIA_WR_2
1517
Sbl_Csia_Wr_3
1517
Register Call Summary for Register SBL_CSIA_WR_3
1518
Sbl_Csib_Wr_0
1518
Register Call Summary for Register SBL_CSIB_WR_0
1518
Sbl_Csib_Wr_1
1519
Register Call Summary for Register SBL_CSIB_WR_1
1519
Sbl_Csib_Wr_2
1519
Register Call Summary for Register SBL_CSIB_WR_2
1520
Sbl_Csib_Wr_3
1520
Register Call Summary for Register SBL_CSIB_WR_3
1520
CAMERA_ISP_CSI2_REGS1 Register Summary
1521
Csi2_Short_Packet
1521
Register Call Summary for Register CSI2_CTRL
1530
Register Call Summary for Register CSI2_DBG_H
1530
Csi2_Dbg_P
1539
Register Call Summary for Register CSI2_DBG_P
1539
Csi2_Ctx_Dat_Pong_Addr
1541
Register Call Summary for Register Csi2_Ctx_Ctrl3
1552
CAMERA_ISP_CSI2_REGS2 Registers Mapping Summary
1552
CAMERA_ISP _CSIPHY Registers Mapping Summary
1553
Csiphy_Reg0
1553
Csiphy_Reg1
1553
Csiphy_Reg2
1553
Display Subsystem Highlight
1561
LCD Interface Signals and Configurations
1566
I/O Pad Mode Selection
1569
LCD Support Parallel Interface (RFBI Mode)
1570
LCD Interface Signals (RFBI Mode)
1570
LCD Support Parallel Interface (Bypass Mode)
1572
LCD Interface Signals (Bypass Mode)
1572
LCD Pixel Data Monochrome4 Passive Matrix
1573
Number of Displayed Pixels Per Pixel Clock Cycle Based on Display Type
1573
LCD Pixel Data Monochrome8 Passive Matrix
1574
LCD Pixel Data Color Passive Matrix
1574
LCD Pixel Data Color12 Active Matrix
1575
LCD Pixel Data Color16 Active Matrix
1576
LCD Pixel Data Color18 Active Matrix
1576
LCD Pixel Data Color24 Active Matrix
1577
RFBI Data Stall Signal Diagram
1577
RFBI Data Stall Signal Diagram with Handcheck
1578
Command Data Write
1578
Programmable Timing Fields in RFBI Mode
1578
Display Data Read
1579
Read to Write and Write to Read
1579
Programmable Fields in Bypass Mode
1579
Active Matrix Timing Diagram of Configuration 1 (Start of Frame)
1580
Active Matrix Timing Diagram of Configuration 1 (between Lines)
1580
Active Matrix Timing Diagram of Configuration 1 (between Frames)
1581
Active Matrix Timing Diagram of Configuration 1 (End of Frame)
1581
Active Matrix Timing Diagram of Configuration 2 (Start of Frame)
1581
Active Matrix Timing Diagram of Configuration 2 (between Lines)
1582
Active Matrix Timing Diagram of Configuration 2 (between Frames)
1582
Active Matrix Timing Diagram of Configuration 2 (End of Frame)
1582
Active Matrix Timing Diagram of Configuration 3 (Start of Frame)
1583
Active Matrix Timing Diagram of Configuration 3 (between Lines)
1583
Active Matrix Timing Diagram of Configuration 3 (between Frames)
1583
Active Matrix Timing Diagram of Configuration 3 (End of Frame)
1583
Passive Matrix Timing Diagram (Start of Frame)
1584
Passive Matrix Timing Diagram (between Lines)
1584
Passive Matrix Timing Diagram (between Frames)
1584
Passive Matrix Timing Diagram (End of Frame)
1584
Typical DSI Connection
1585
I/O Description for DSI Serial Interface
1585
DSI Lane Configuration
1586
Video Interface for DSI Protocol Engine
1587
Video Interface in the Context of Video Mode
1588
DSI Video Mode Without Burst (No-Line Buffer)
1590
DSI Video Mode Without Burst (One-Line Buffer)
1591
DSI Video Mode with Burst (Two-Line Buffers)
1592
Video Interface in the Context of Command Mode
1593
Stall Timing with Pixel on Rising Edge
1594
Stall Timing with Pixel on Falling Edge
1594
Data Flow in Command Mode Using the Video Port
1595
Two Data Lane Configuration
1596
One Data Lane Configuration
1596
Two Packets Using Two-Data Lane Configuration (Example)
1597
Protocol Layer with Short and Long Packets
1597
Short Packet Structure
1598
Long Packet Structure
1598
Data Identifier Structure
1599
Virtual Channel Controller
1599
Pixel Data Format in Video Mode
1600
Synchronization Codes
1600
Sync Short Packet Values
1601
DSI Video Mode: Nonburst Transfer with VE and HE
1602
DSI Video Mode: Nonburst Transfer Without VE and HE
1603
DSI Video Mode: Burst Transfer Without VE and HE
1604
DSI General Frame Structure
1605
DSI General Frame Structure Using Burst Mode
1606
Dsi General Frame Structure Using Burst Mode and Interleaving
1607
Virtual Channel Values
1608
Bits Per Pixel RGB Color Format, Long Packet
1609
Bits Per Pixel (Loosely Packed) RGB Color Format, Long Packet
1610
Bits Per Pixel (Packed) RGB Color Format, Long Packet
1611
Bits Per Pixel RGB Color Format, Long Packet
1612
TV Display Interface (S-Video Mode, DC Coupled, High FS Swing)
1613
TV Display Interface (Composite Mode, DC Coupled, High FS Swing)
1613
TV Display Interface (Composite Mode, AC Coupled, Low FS Swing)
1614
TV Display Interface (Bypass Mode, Dual Channel)
1614
TV Display Interface Pins
1615
Typical Values for Rout, Rset and Cout
1615
Display Subsystem Integration
1618
Display Subsystem Clock Tree
1619
Display Subsystem Clocks
1620
Possible Digital Clock Division for the Video Encoder
1622
Display Subsystem DMA Tree
1628
DSS DMA Requests Description
1628
DSI Interrupt Tree
1629
DISPC and DSS Interrupts Tree
1630
Display Subsystem Interrupts
1630
DSI Global Interrupts
1631
DSI Complex I/O Interrupts
1632
DSI Virtual Channel Interrupts
1633
Display Subsystem Full Schematic
1634
Display Controller Architecture Overview
1635
Palette/Gamma Correction Architecture
1639
Ycbcr 4:2:2 to Ycbcr 4:4:4 (0- or 180-Degree Rotation)
1642
Ycbcr 4:2:2 to Ycbcr 4:4:4 (90- or 270-Degree Rotation)
1642
Interpolation of the Missing Chrominance Component
1642
Ycbcr to RGB Registers (VIDFULLRANGE = 0)
1643
Ycbcr to RGB Registers (VIDFULLRANGE = 1)
1643
Color Space Conversion Macro-Architecture
1644
Video Upsampling
1645
Dispc_Vidn_Picture_Size
1645
Resampling Macro-Architecture (3-Coefficient Processing)
1646
Functional Clock Frequency Requirement in RGB16 & YUV4:2:2-Active Matrix Display
1647
Functional Clock Frequency Requirement in RGB24-Active Matrix Display
1647
Overlay Manager in Normal Mode
1648
Display Attributes in Normal Mode
1649
Overlay Manager in Alpha Mode
1650
Display Attributes in Alpha Mode
1650
Alpha Blending Macro Architecture with Pre-Multiplied Alpha Support
1651
Alpha Blending 4-Bit Values
1652
Video Source Transparency Example
1653
Graphics Destination Transparency Example
1654
Color Phase Rotation Matrix
1655
Color Phase Rotation Macro Architecture
1655
Maximum Width Allowed
1657
DSI Protocol Engine
1659
DSI Transmitter/Receiver Data Flow
1660
LP to HS Timing
1661
LP to HS Timing Parameters
1661
Dsi_Phy_Register0
1661
HS to LP Timing
1662
Dsi_Clk_Timing
1662
Dsi_Vm_Timing7
1662
HS to LP Timing Parameters
1663
Extra NULL Packet Header
1663
Extra NULL Packet Payload
1664
Dsi_Vcn_Irqenable
1665
Dsi_Vm_Timing4
1666
Dsi_Vm_Timing6
1666
HS Command Mode Interleaving
1667
LP Command Mode Interleaving
1669
Complex I/O Power FSM
1672
Dsi_Complexio_Cfg1
1672
DSI PLL Power FSM
1673
DSI PLL HS Clock FSM
1674
Forcetxstopmode FSM
1676
Turnrequest FSM
1677
Dsi_Timing1
1677
High-Speed TX Timer FSM
1678
Dsi_Timing2
1678
Low-Power RX Timer FSM
1679
Dsi_Phy_Register4
1681
Checksum Transmission
1683
Bit CRC Generation Using a Shift Register
1684
Dsi_Pll_Control
1684
DSI PLL Controller Overview
1685
DSI PLL Reference Diagram
1686
DSI PLL Operation Modes When Not Locked
1686
RFBI Architecture Overview
1688
Read/Write Function Description
1690
Minimum Cycle Time for Csx/We Always Asserted
1690
Rfbi_Configi
1690
Video Encoder Architecture Overview
1691
VENC_S_CARR Register Recommended Values
1692
Venc_S_Carr
1692
Closed-Caption Data Format
1693
Closed Captioning Timing
1694
Closed-Caption Run Clock Frequency Settings
1694
Closed-Caption Standard Timing Values
1694
Venc_Cc_Carr_Wss_Carr
1694
Wide-Screen Signaling Run Clock Frequency Settings
1695
WSS Timing
1696
Video DAC Stage Architecture
1697
Analog TV Output Control
1697
DC-Coupling TV Detect Waveforms for TV Connected and Disconnected
1700
AC-Coupling TV Detect Waveforms for TV Connected and Disconnected
1701
GPIO Signal Waveform Proposal for TV Detection/Disconnection in DC-Coupling Mode
1702
GPIO Signal Waveform Proposal for TV Detection/Disconnection in AC-Coupling Mode
1702
DAC Test Mode in Composite Video Mode
1703
Venc_Output_Test
1703
DAC Test Mode in Separate Video Mode
1704
Venc_Output_Control
1704
Video DAC Stage Power Management
1705
Shadow Registers
1707
Overlay Optimization: Case
1711
Dispc_Gfx_Size
1711
Dispc_Gfx_Row_Inc
1711
Dispc_Gfx_Window_Skip
1711
Overlay Optimization: Case
1712
Overlay Optimization: Case
1713
Dispc_Gfx_Attributes
1713
Vertical/Horizontal Accumulator Phase
1717
Color Space Conversion Register Values
1718
Rotation/Mirroring Settings
1722
DMA Rotation Register Settings
1722
Video Rotation Register Settings (with RGB24 Packet Format)
1723
Register Settings for DMA Rotation with Mirroring
1724
VRFB Rotation - DMA Settings
1724
Offset for VRFB Rotation
1725
VRFB Rotation with Mirroring - DMA Settings
1726
Offset for VRFB Rotation with Mirroring
1727
Video Rotation Register Settings (YUV Only)
1727
Video Rotation with Mirroring Register Settings (YUV Only)
1728
Dispc_Vidn_Attributes
1728
Dispc_Vidn_Conv_Coef0
1729
Timing Values Description (Active Matrix Display)
1730
Programming Rules
1730
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Active Matrix Display
1731
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - Mono4
1731
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - Mono8
1731
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - Color
1731
Pcdmin Formulas (V Down-Sampling Only)
1732
Dispc_Size_Lcd
1732
Dispc_Vidn_Size
1732
Color Phase Rotation Matrix
1734
Color Phase Rotation Matrix (R Component Only)
1734
Color Phase Rotation Matrix (G Component Only)
1734
Color Phase Rotation Matrix (B Component Only)
1734
Diagonal Matrix Configuration
1735
Example - Diagonal Matrix Configuration
1735
Image with and Without CPR (Diagonal Matrix)
1736
Example - Image with and Without CPR (Standard Matrix)
1737
Register Access Width Limitations
1739
Virtual Channel TX FIFO Size Values
1743
Dsi_Ctrl
1743
Virtual Channel TX FIFO Start Address
1744
Virtual Channel RX FIFO Size Values
1745
Virtual Channel RX FIFO Start Address
1745
DSI PLL Programming Blocks
1751
DSI PLL Go Sequence (Manual Mode)
1752
DSI PLL Go Sequence (Automatic Mode)
1753
Dsi_Pll_Go
1753
Gated Mode Sequence
1754
DSI PLL Programming Sequence
1755
Recommended Programming Values
1757
High-Speed Clock Transmission
1759
High-Speed Data Transmission
1761
Turn-Around Request in Transmit Mode
1762
Turn-Around Request in Receive Mode
1763
Dispc_Control
1764
Rfbi_Control
1764
RFBI Behavior
1765
RFBI Timings Configuration
1769
How to Use RFBI
1771
RFBI Initial Configuration
1772
RFBI Output Enable
1773
Analog TV Output Modes
1774
Video Encoder Register Programming Values
1775
Venc_F_Control
1775
Venc_Vidout_Ctrl
1775
Venc_Sync_Ctrl
1775
Venc_Llen
1775
Venc_Flens
1775
Venc_Hfltr_Ctrl
1775
Venc_C_Phase
1775
Venc_Black_Level
1775
Venc_Blank_Level
1775
Vertical Filtering Macro Architecture (Three Taps)
1777
Vertical Filtering Macro Architecture (Five Taps)
1778
Horizontal Filtering Macro Architecture (Five Taps)
1779
Vertical Up-/Down-Sampling Algorithm
1780
Horizontal Up-/Down-Sampling Algorithm
1781
Vertical FIR Coefficients Corresponding Table (3-Tap Configuration)
1781
Horizontal FIR Coefficients Corresponding Table (5-Tap Configuration)
1782
Vertical/Horizontal Accumulator Phase
1784
Up-Sampling Vertical Filter Coefficients (Three Taps)
1785
Up-Sampling Vertical Filter Coefficients (Five Taps)
1785
Up-Sampling Horizontal Filter Coefficients (Five Taps)
1785
Down-Sampling Vertical Filter Coefficients (Three Taps)
1786
Down-Sampling Vertical Filter Coefficients (Five Taps)
1787
Down-Sampling Horizontal Filter Coefficients (Five Taps)
1787
QVGA LCD Timings
1792
DSI Clock Tree in Video Mode
1793
Main Steps
1796
PRCM Registers
1797
DSI PLL Configuration Registers
1797
Dsi_Sysconfig
1797
Dsi_Irqstatus
1797
Dsi_Clk_Ctrl
1797
DSI Control Registers
1798
Dss_Control
1798
Dsi_Irqenable
1798
DSI Complex I/O Registers
1799
DSI Timing Registers
1799
DSI Control Registers
1799
Dsi_Sysstatus
1799
Dsi_Complexio_Irqstatus
1799
Dsi_Complexio_Irqenable
1799
Dsi_Vm_Timing1
1799
Drive Stop State
1800
Dsi_Phy_Register1
1800
Dsi_Phy_Register2
1800
Reset DISPC
1801
Configure DISPC Registers
1801
Configure Color Space Coefficient Registers
1801
Dispc_Sysconfig
1801
Dispc_Irqenable
1801
Configure DISPC_CONTROL
1802
Enable DISPC
1802
Main Sequence
1803
Configure DSS Clocks at the PRCM Module
1804
Configure DSI Protocol Engine, DSI PLL, and Complex I/O
1804
Reset DSI Modules
1804
Configure DSI PLL
1805
Switch to DSI PLL Clock Source
1806
DSI Complex I/O Registers
1806
DSI Timing Registers
1807
Dsi_Tx_Fifo_Vc_Size
1808
Dsi_Rx_Fifo_Vc_Size
1808
Configure DSI_PHY Timing
1809
Drive Stop State
1809
Initialization of the External MIPI LCD Controller
1809
Reset DISPC
1809
Configure DISPC Registers
1810
Enable Command Mode and Automatic TE
1810
Dispc_Divisor
1810
Send Frame Data to LCD Panel Using Automatic TE
1811
Display Subsystem Instance Summary
1812
Display Subsystem Register Mapping Summary
1812
Display Controller Register Mapping Summary
1812
Dss_Sysconfig
1812
Dss_Sysstatus
1812
Dss_Irqstatus
1812
Dss_Clk_Status
1812
Dispc_Revision
1812
Dispc_Sysstatus
1812
Dispc_Irqstatus
1812
Display Controller VID1 Register Mapping Summary
1813
Dispc_Global_Alpha
1813
Dispc_Size_Dig
1813
Dispc_Gfx_Baj
1813
Dispc_Gfx_Position
1813
Dispc_Gfx_Fifo_Threshold
1813
Dispc_Gfx_Fifo_Size_Status
1813
Dispc_Gfx_Pixel_Inc
1813
Dispc_Gfx_Table_Ba
1813
Dispc_Vidn_Baj
1813
Display Controller VID2 Register Mapping Summary
1814
RFBI Register Mapping Summary
1814
Dispc_Vidn_Preload
1814
Video Encoder Register Mapping Summary
1815
Rfbi_Sysstatus
1815
Rfbi_Pixel_Cnt
1815
Rfbi_Line_Number
1815
Rfbi_Cmd
1815
Rfbi_Param
1815
Rfbi_Read
1815
Rfbi_Status
1815
Rfbi_Onoff_Timei
1815
Rfbi_Cycle_Timei
1815
DSI Protocol Engine Register Mapping Summary
1816
Venc_Gen_Ctrl
1816
Dsi_Revision
1816
Dsi_Vm_Timing2
1816
Dsi_Vm_Timing3
1816
DSI_PHY Register Mapping Summary
1817
DSI PLL Controller Register Mapping Summary
1817
Dsi_Vm_Timing5
1817
Dsi_Stopclk_Timing
1817
Dsi_Vcn_Ctrl
1817
Dsi_Vcn_Te
1817
Dsi_Vcn_Irqstatus
1817
Dsi_Phy_Register3
1817
Dsi_Phy_Register5
1817
Dsi_Pll_Status
1817
Dss_Revisionnumber
1818
Register Call Summary for Register DSS_REVISIONNUMBER
1818
Dispc_Default_Color_M
1836
Register Call Summary for Register Dispc_Default_Color_M
1836
Dispc_Trans_Color_M
1836
Type
1836
Register Call Summary for Register Dispc_Trans_Color_M
1837
Register Call Summary for Register DISPC_LINE_NUMBER
1838
Dispc_Timing_H
1838
Register Call Summary for Register DISPC_TIMING_H
1838
Dispc_Timing_V
1838
Register Call Summary for Register DISPC_TIMING_V
1839
Dispc_Cpr_Coef_R
1865
Register Call Summary for Register DISPC_CPR_COEF_R
1865
Dispc_Cpr_Coef_G
1865
Register Call Summary for Register DISPC_CPR_COEF_G
1866
Dispc_Cpr_Coef_B
1866
Register Call Summary for Register DISPC_CPR_COEF_B
1866
Register Call Summary for Register RFBI_PARAM
1873
Rfbi_Data
1878
Register Call Summary for Register RFBI_DATA
1878
Rfbi_Data_Cycle2_I
1879
Register Call Summary for Register Rfbi_Data_Cycle2_I
1879
Rfbi_Data_Cycle3_I
1880
Register Call Summary for Register Rfbi_Data_Cycle3_I
1880
Register Call Summary for Register VENC_F_CONTROL
1884
Venc_Gain_U
1888
Register Call Summary for Register VENC_GAIN_U
1888
Venc_Gain_V
1888
Register Call Summary for Register VENC_GAIN_V
1889
Venc_Gain_Y
1889
Register Call Summary for Register VENC_GAIN_Y
1889
Venc_Hs_Int_Start_Stop_X
1898
Register Call Summary for Register VENC_HS_INT_START_STOP_X
1898
Venc_Hs_Ext_Start_Stop_X
1899
Register Call Summary for Register VENC_HS_EXT_START_STOP_X
1899
Venc_Vs_Int_Start_X
1899
Register Call Summary for Register VENC_VS_INT_START_X
1899
Venc_Vs_Int_Stop_X_Vs_Int_Start_Y
1900
Register Call Summary for Register VENC_VS_INT_STOP_X_VS_INT_START_Y
1900
Venc_Vs_Int_Stop_Y_Vs_Ext_Start_X
1900
Register Call Summary for Register VENC_VS_INT_STOP_Y_VS_EXT_START_X
1900
Venc_Vs_Ext_Stop_X_Vs_Ext_Start_Y
1901
Register Call Summary for Register VENC_VS_EXT_STOP_X_VS_EXT_START_Y
1901
Venc_Vs_Ext_Stop_Y
1901
Register Call Summary for Register VENC_VS_EXT_STOP_Y
1901
Venc_Avid_Start_Stop_X
1902
Register Call Summary for Register VENC_AVID_START_STOP_X
1902
Venc_Avid_Start_Stop_Y
1902
Register Call Summary for Register VENC_AVID_START_STOP_Y
1902
Venc_Fid_Int_Start_X_Fid_Int_Start_Y
1903
Register Call Summary for Register VENC_FID_INT_START_X_FID_INT_START_Y
1903
Venc_Fid_Int_Offset_Y_Fid_Ext_Start_X
1903
Register Call Summary for Register VENC_FID_INT_OFFSET_Y_FID_EXT_START_X
1903
Venc_Fid_Ext_Start_Y_Fid_Ext_Offset_Y
1904
Register Call Summary for Register VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y
1904
Venc_Tvdetgp_Int_Start_Stop_X
1904
Register Call Summary for Register VENC_TVDETGP_INT_START_STOP_X
1904
Venc_Tvdetgp_Int_Start_Stop_Y
1905
Register Call Summary for Register VENC_TVDETGP_INT_START_STOP_Y
1905
Register Call Summary for Register DSI_IRQSTATUS
1914
Register Call Summary for Register DSI_CTRL
1919
Dsi_Vcn_Long_Packet_Header
1946
Dsi_Pll_Configuration1
1961
Register Call Summary for Register DSI_PLL_CONFIGURATION1
1962
Dsi_Pll_Configuration2
1962
Register Call Summary for Register DSI_PLL_CONFIGURATION2
1963
Graphics Accelerator Highlight
1966
SGX Subsystem Integration
1969
Clock Descriptions
1969
SGX Block Diagram
1971
SGX Instance Summary
1973
SGX Registers Mapping Summary
1973
Ocp_Revision
1974
Ocp_Irqstatus_Raw_0
1975
Register Call Summary for Register OCP_IRQSTATUS_RAW_0
1976
Ocp_Irqstatus_Raw_1
1976
Register Call Summary for Register OCP_IRQSTATUS_RAW_1
1976
Ocp_Irqstatus_Raw_2
1977
Register Call Summary for Register OCP_IRQSTATUS_RAW_2
1977
Ocp_Irqstatus_0
1977
Register Call Summary for Register OCP_IRQSTATUS_0
1978
Ocp_Irqstatus_1
1978
Register Call Summary for Register OCP_IRQSTATUS_1
1978
Ocp_Irqstatus_2
1979
Register Call Summary for Register OCP_IRQSTATUS_2
1979
Ocp_Irqenable_Set_0
1979
Register Call Summary for Register OCP_IRQENABLE_SET_0
1980
Ocp_Irqenable_Set_1
1980
Register Call Summary for Register OCP_IRQENABLE_SET_1
1980
Ocp_Irqenable_Set_2
1981
Register Call Summary for Register OCP_IRQENABLE_SET_2
1981
Ocp_Irqenable_Clr_0
1981
Register Call Summary for Register OCP_IRQENABLE_CLR_0
1982
Ocp_Irqenable_Clr_1
1982
Register Call Summary for Register OCP_IRQENABLE_CLR_1
1982
Ocp_Irqenable_Clr_2
1983
Register Call Summary for Register OCP_IRQENABLE_CLR_2
1983
MCMD Qualifier Description
1993
Mreqinfo Qualifier Description
1993
Sresp Qualifier Description
1993
Interconnect Architecture Overview
1995
L3 Initiator Agents
1996
L3 Target Agents
1996
L4-Core Initiator Agent
1997
L4-Core Target Agents
1997
L4-Per Initiator Agent
1998
L4-Per Target Agents
1998
L4-Emu Initiator Agents
1998
L4-Emu Target Agents
1998
L4-Wakeup Initiator Agent
1999
L4-Wakeup Target Agents
1999
Connectivity Matrix
1999
L4-Emu Target Agents
1999
L3 Interconnect Overview
2001
L3 Interconnect Clocks
2002
L3 Interconnect Reset
2002
L3 Interconnect Power Domain
2002
L3 Interconnect Hardware Requests
2003
Initiatorid Definition
2003
Target Firewall and Region Configuration
2004
Flow Chart of the Protection Mechanism
2005
L3 Firewall Implementation
2006
L3 Firewall Size Parameter Definition
2007
L3 Region Overlay and Priority Level Overview
2009
Mreqinfo Parameter Combinations
2010
Example of REQ_INFO_PERMISSION Register
2011
L3 Firewall Permission-Setting Registers
2011
L3 Firewall Error Logging Registers
2012
L3 Error Reporting Structure
2014
Error Types
2015
CODE Field Definition
2015
L3_Ta_Error_Log
2015
L3 Timeout Register Target and Agent Programming
2016
L3_Ia_Error_Log
2016
L3_Ta_Agent_Control
2016
Global Error Routing
2018
L3 External Input Flags
2018
L3 Error Routing
2019
L3_SI_FLAG_STATUS_0 for Application Error
2019
L3_SI_FLAG_STATUS_1 for Debug Error
2020
Typical Error Analysis Sequence
2022
L3_Ia_Error_Log_Addr
2022
Error Clearing
2024
L3_Ia_Agent_Status
2024
Mreqinfo Parameter Example
2025
Firewall Configuration Solution
2026
Firewall Configuration Solution
2027
Instance Summary
2028
Initiator Agent Common Register Summary
2029
L3_Ia_Agent_Control
2031
Target Agent Common Register Summary
2035
Target Agent Common Register Summary
2036
RT Register Summary
2041
Protection Mechanism Common Register Summary
2043
L3_Pm_Error_Log
2043
L3_Pm_Control
2043
L3_Pm_Error_Clear_Single
2043
L3_Pm_Error_Clear_Multi
2043
Protection Mechanism Common Register Summary
2044
L3_Pm_Req_Info_Permission_I
2047
Register Call Summary for Register L3_Pm_Req_Info_Permission_I
2047
L3_Pm_Read_Permission_I
2048
Register Call Summary for Register L3_Pm_Read_Permission_I
2048
L3_Pm_Write_Permission_I
2049
Register Call Summary for Register L3_Pm_Write_Permission_I
2049
L3_Pm_Addr_Match_K
2051
Register Call Summary for Register L3_Pm_Addr_Match_K
2051
Reset Value for L3_Pm_Addr_Match_K
2052
Register Summary
2052
L3_Si_Flag_Status_0
2053
Register Call Summary for Register L3_SI_FLAG_STATUS_0
2054
L3_Si_Flag_Status_1
2054
Register Call Summary for Register L3_SI_FLAG_STATUS_1
2054
L4 Interconnect Overview
2056
L4 Initiator-Target Connectivity for L4-Core and L4-Per
2056
L4-Core Target Agents
2057
L4-Per Target Agents
2057
L4-Emu Initiator Agents
2059
L4-Wakeup Target Agents
2059
L4-Wakeup Initiator Agents
2059
L4 Interconnect Clocks
2060
L4 Interconnect Hardware Reset
2060
L4 Interconnect Power Domains
2060
L4 Firewall Overview
2064
Region Allocation for L4-Core Interconnect
2064
Region Allocation for L4-Per Interconnect
2067
Region Allocation for L4-Emu Interconnect
2068
L4 Firewall Register Description Overview
2069
L4 Time-Out Link and TA Programming
2071
L4 Time-Out TA Programming
2071
L4 Error Reporting
2073
Global Initialization of Surrounding Modules
2073
Typical Error Analysis Sequence
2075
Typical Error Analysis Sequence
2076
Main Sequence - Error Analysis Mode
2076
Subprocess Call Summary for Main Sequence - Error Analysis Mode
2076
Protection Violation Error Identification
2077
Unsupported Command/Address Hole Error Identification
2077
Reset TA and Module
2077
Time-Out Configuration
2078
Firewall Configuration
2078
L4-Core Instance Summary
2078
L4-Per Instance Summary
2079
L4-Emu Instance Summary
2080
L4-WKUP Instance Summary
2080
L4 IA Register Summary
2080
L4 IA Register Summary
2081
L4_Ia_Component_L
2081
Register Call Summary for Register L4_IA_COMPONENT_L
2081
L4_Ia_Component_H
2081
Register Call Summary for Register L4_IA_COMPONENT_H
2082
L4_Ia_Core_L
2082
Register Call Summary for Register L4_IA_CORE_L
2082
L4_Ia_Core_H
2082
Register Call Summary for Register L4_IA_CORE_H
2082
L4_Ia_Agent_Control_L
2083
Register Call Summary for Register L4_IA_AGENT_CONTROL_L
2083
L4_Ia_Agent_Control_H
2083
Register Call Summary for Register L4_IA_AGENT_CONTROL_H
2083
L4_Ia_Agent_Status_L
2084
Register Call Summary for Register L4_IA_AGENT_STATUS_L
2084
L4_Ia_Agent_Status_H
2084
Register Call Summary for Register L4_IA_AGENT_STATUS_H
2084
L4_Ia_Error_Log_L
2085
Register Call Summary for Register L4_IA_ERROR_LOG_L
2085
L4_Ia_Error_Log_H
2085
Register Call Summary for Register L4_IA_ERROR_LOG_H
2085
CORE_TA Common Register Summary
2086
CORE_TA Common Register Summary
2087
CORE_TA Common Register Summary
2088
CORE_TA Common Register Summary
2089
PER_TA Common Register Summary
2090
PER_TA Common Register Summary
2091
EMU_TA Common Register Summary
2091
EMU_TA Common Register Summary
2092
WKUP_TA Common Register Summary
2092
L4_Ta_Component_L
2093
Register Call Summary for Register L4_TA_COMPONENT_L
2093
L4_Ta_Component_H
2093
Register Call Summary for Register L4_TA_COMPONENT_H
2093
L4_Ta_Core_L
2093
Register Call Summary for Register L4_TA_CORE_L
2094
L4_Ta_Core_H
2094
Register Call Summary for Register L4_TA_CORE_H
2094
L4_Ta_Agent_Control_L
2094
Register Call Summary for Register L4_TA_AGENT_CONTROL_L
2095
L4_Ta_Agent_Control_H
2095
Register Call Summary for Register L4_TA_AGENT_CONTROL_H
2095
L4_Ta_Agent_Status_L
2095
Register Call Summary for Register L4_TA_AGENT_STATUS_L
2096
L4_Ta_Agent_Status_H
2096
Register Call Summary for Register L4_TA_AGENT_STATUS_H
2096
L4 LA Register Summary
2096
L4_La_Component_L
2097
Register Call Summary for Register L4_LA_COMPONENT_L
2097
L4_La_Component_H
2097
Register Call Summary for Register L4_LA_COMPONENT_H
2097
L4_La_Network_L
2097
Register Call Summary for Register L4_LA_NETWORK_L
2098
L4_La_Network_H
2098
Register Call Summary for Register L4_LA_NETWORK_H
2098
L4_La_Initiator_Info_L
2098
Register Call Summary for Register L4_LA_INITIATOR_INFO_L
2098
Reset Value for L4_LA_INITIATOR_INFO_L
2099
L4_La_Initiator_Info_H
2099
Register Call Summary for Register L4_LA_INITIATOR_INFO_H
2099
Reset Value for L4_LA_INITIATOR_INFO_H
2099
L4_La_Network_Control_L
2100
Register Call Summary for Register L4_LA_NETWORK_CONTROL_L
2100
L4_La_Network_Control_H
2100
Register Call Summary for Register L4_LA_NETWORK_CONTROL_H
2101
L4 AP Register Summary
2101
L4 AP Register Summary
2102
L4_Ap_Component_L
2102
Register Call Summary for Register L4_AP_COMPONENT_L
2102
L4_Ap_Component_H
2103
Register Call Summary for Register L4_AP_COMPONENT_H
2103
L4_Ap_Segment_I_L
2103
Register Call Summary for Register L4_Ap_Segment_I_L
2103
L4_Ap_Segment_I_L Reset Values
2103
Register Call Summary for Register L4_Ap_Region_L_H
2108
Reset Values for CORE_AP L4_Ap_Region_L_L and L4_Ap_Region_L_H
2108
Reset Values for PER_AP L4_Ap_Region_L_L and L4_Ap_Region_L_H
2110
Reset Values for EMU_AP L4_Ap_Region_L_L and L4_Ap_Region_L_H
2111
Reset Values for WKPUP_AP L4_Ap_Region_L_L and L4_Ap_Region_L_H
2112
GPMC Environment
2114
GPMC to 16-Bit Address/Data-Multiplexed Memory
2115
GPMC to 16-Bit NAND Device
2116
GPMC I/O Description
2116
GPMC Pin Multiplexing Options
2117
GPMC Integration in the Device
2118
Gpmc_Config1_I
2120
GPMC Functional Diagram
2122
Gpmc_Ecc_Config
2123
Chip-Select Address Mapping and Decoding Mask
2125
Asynchronous Single Read on a Nonmultiplexed Address/Data Device
2129
Wait Behavior During an Asynchronous Single Read Access (Gpmcfclkdivider = 1)
2135
Wait Behavior During a Synchronous Read Burst Access
2137
Idle Cycle Insertion Configuration
2139
Asynchronous Single Read on an Address/Data-Nonmultiplexed Device
2141
Asynchronous Single Read on an Address/Data-Multiplexed Device
2142
Asynchronous Single Write on an Address/Data-Nonmultiplexed Device
2144
Asynchronous Single Write on an Address/Data-Multiplexed Device
2145
Asynchronous Multiple (Page Mode) Read
2146
Synchronous Single Read (GPMCFCLKDIVIDER = 0)
2148
Synchronous Single Read (GPMCFCLKDIVIDER = 1)
2149
Synchronous Single Write on an Address/Data-Multiplexed Device
2150
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0)
2151
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1)
2152
Synchronous Multiple (Burst) Write
2153
Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode
2155
Chip-Select Configuration for NAND Interfacing
2157
NAND Command Latch Cycle
2159
NAND Address Latch Cycle
2159
NAND Data Read Cycle
2160
NAND Data Write Cycle
2161
Gpmc_Status
2162
ECC Enable Settings
2164
Gpmc_Ecc_Size_Config
2164
Hamming Code Accumulation Algorithm
2165
Hamming Code Accumulation Algorithm
2166
ECC Computation for a 256-Byte Data Stream (Read or Write)
2166
ECC Computation for a 512-Byte Data Stream (Read or Write)
2167
Word16 ECC Computation
2168
Flattened BCH Codeword Mapping (512 Bytes + 104 Bits)
2169
Aligned Message Byte Mapping in 8-Bit NAND
2170
Aligned Message Byte Mapping in 16-Bit NAND
2170
Aligned Nibble Mapping of Message in 8-Bit NAND
2170
Misaligned Nibble Mapping of Message in 8-Bit NAND
2171
Aligned Nibble Mapping of Message in 16-Bit NAND
2171
Misaligned Nibble Mapping of Message in 16-Bit NAND (1 Unused Nibble)
2171
Misaligned Nibble Mapping of Message in 16-Bit NAND (2 Unused Nibbles)
2171
Misaligned Nibble Mapping of Message in 16-Bit NAND (3 Unused Nibbles)
2171
Manual Mode Sequence and Mapping
2173
NAND Page Mapping and ECC: Per-Sector Schemes
2177
NAND Page Mapping and ECC: Pooled Spare Schemes
2178
NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC
2179
Prefetch Mode Configuration
2181
Gpmc_Prefetch_Config1
2181
Gpmc_Prefetch_Config2
2181
Gpmc_Prefetch_Control
2181
Write-Posting Mode Configuration
2183
NAND Read Cycle Optimization Timing Description
2185
GPMC Signals
2186
GPMC Connection to an External nor Flash Memory
2187
Useful Timing Parameters on the Memory Side
2187
Calculating GPMC Timing Parameters
2188
Synchronous Burst Read Access (Timing Parameters in Clock Cycles)
2189
AC Characteristics for Asynchronous Read Access
2189
Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
2190
GPMC Timing Parameters for Asynchronous Read Access
2190
AC Characteristics for Asynchronous Single Write ( Memory Side)
2190
Asynchronous Single Write Access (Timing Parameters in Clock Cycles)
2191
GPMC Timing Parameters for Asynchronous Single Write
2191
Supported Memory Interfaces
2192
NAND Interface Bus Operations Summary
2193
NOR Interface Bus Operations Summary
2194
GPMC Instance Summary
2195
GPMC Registers Mapping Summary
2195
Gpmc_Revision
2195
Gpmc_Sysstatus
2195
Gpmc_Irqstatus
2195
Gpmc_Irqenable
2195
Gpmc_Timeout_Control
2195
Gpmc_Err_Address
2195
Gpmc_Prefetch_Status
2195
Gpmc_Ecc_Control
2195
Gpmc_Err_Type
2201
Gpmc_Config
2204
Register Call Summary for Register GPMC_CONFIG
2206
Gpmc_Config2_I
2206
Register Call Summary for Register Gpmc_Config2_I
2207
Gpmc_Config3_I
2207
Register Call Summary for Register Gpmc_Config3_I
2208
Gpmc_Config4_I
2208
Register Call Summary for Register Gpmc_Config4_I
2209
Gpmc_Config5_I
2209
Register Call Summary for Register Gpmc_Config5_I
2210
Gpmc_Config6_I
2210
Register Call Summary for Register Gpmc_Config6_I
2211
Gpmc_Config7_I
2211
Register Call Summary for Register Gpmc_Config7_I
2212
Gpmc_Nand_Command_I
2212
Register Call Summary for Register Gpmc_Nand_Command_I
2212
Gpmc_Nand_Address_I
2212
Register Call Summary for Register Gpmc_Nand_Address_I
2213
Gpmc_Nand_Data_I
2213
Register Call Summary for Register Gpmc_Nand_Data_I
2213
Gpmc_Bch_Result0_I
2221
Register Call Summary for Register Gpmc_Bch_Result0_I
2221
Gpmc_Bch_Result1_I
2221
Register Call Summary for Register Gpmc_Bch_Result1_I
2221
Gpmc_Bch_Result2_I
2222
Register Call Summary for Register Gpmc_Bch_Result2_I
2222
Gpmc_Bch_Result3_I
2222
Register Call Summary for Register Gpmc_Bch_Result3_I
2222
SDRC Subsystem Environment
2224
SDRC Subsystem Connections to SDR SDRAM
2226
SDRC Subsystem Connections to DDR SDRAM
2227
SDRC Subsystem I/O Description
2227
SDRC SDR/DDR-SDRAM System Address Multiplexing Schemes (1 of 3)
2231
SDRC Integration to the Device
2234
SMS Top-Level Diagram
2237
Arbitration Class Allocation
2238
Sms_Class_Arbiter1
2239
Reqinfo Parameters Ordering
2241
Region Organization
2243
VRFB Contexts Virtual Address Spaces Vs Rotation Angle
2244
SDRC Architecture
2247
CS0/CS1 Chip-Select Start Address Slots
2248
SDRAM Controller Block Diagram
2250
Address Multiplexing Scheme According to BANKALLOCATION
2251
Simplified View of Bank-Row-Column Vs Row-Bank-Column Bank Allocation
2252
Mobile DDR SDRAM AC Timing Parameters
2252
SDRC Data Lane Configurations
2253
Data Multiplexing Scheme
2254
Data Demultiplexing Scheme
2255
Dynamic Power Saving Configurations
2258
Generic DDR Data-Write and Data-Read Waveforms
2261
Required Synchronization DFF Input Signals
2261
DLL/CDL Architecture
2262
Simplified DLL/CDL Block Diagram
2263
Natural Scan Order
2266
Memory Configuration
2268
Programmable AC Parameters
2268
Nonprogrammable AC Parameters
2269
Sdrc_Dlla_Ctrl
2270
SDRC Subsystem Overview
2278
YUV Format: Pixel Representation
2279
VRFB Context Configuration
2280
Example of VRFB Context 1 Configuration
2281
Calculating Image Size
2282
Display a Rotated QVGA Image
2283
Sms_Rot_Controln
2284
Sms_Rot_Sizen
2284
Sms_Rot_Physical_Ban
2284
Arbitration Granularity Versus Arbitration Decision
2286
Sms_Class_Arbiter2
2286
BURST-COMPLETE on Class 2-Group
2287
Priority between Classes
2288
Sms_Interclass_Arbiter
2288
Idle Cycle Mechanism Within a Burst
2289
Example of EXTENDEDGRANT Mechanism
2290
Arbitration between Classes
2291
Arbitration Within a Class
2292
Generic Arbitration Decision
2293
Arbitration Granularity
2294
SDRC Address Space in MPU Global Address Space
2295
SDRC and SMS Configuration Register Space
2295
VRFB Contexts Vs Rotation Angle
2296
Sdrc_Cs_Cfg
2297
CS Start and End Address Configuration Example
2298
SDRAM Vs SDRC Controller Characteristics
2300
SMS Instance Summary
2301
SMS Register Summary
2301
Sms_Revision
2301
Sms_Sysconfig
2301
Sms_Sysstatus
2301
Sms_Class_Arbiter0
2301
Sms_Err_Addr
2301
Sms_Err_Type
2301
Sms_Pow_Ctrl
2301
SDRC Instance Summary
2314
SDRC Register Summary
2314
Sdrc_Mcfg_P
2323
Register Call Summary for Register Sdrc_Mcfg_P
2324
Sdrc_Mr_P
2326
Register Call Summary for Register Sdrc_Mr_P
2327
Sdrc_Emr2_P
2327
Register Call Summary for Register Sdrc_Emr2_P
2328
Sdrc_Actim_Ctrla_P
2328
Register Call Summary for Register Sdrc_Actim_Ctrla_P
2328
Sdrc_Actim_Ctrlb_P
2328
Register Call Summary for Register Sdrc_Actim_Ctrlb_P
2329
Sdrc_Rfr_Ctrl_P
2329
Register Call Summary for Register Sdrc_Rfr_Ctrl_P
2330
Sdrc_Manual_P
2330
Register Call Summary for Register Sdrc_Manual_P
2330
OCM Subsystem Overview
2331
OCM Subsystem Integration to the Device
2332
SDMA Overview
2337
External SDMA Request Signals
2338
External SDMA Requests Typical Application
2339
Edge-Sensitive DMA Request Scheme
2340
Transition-Sensitive DMA Request Scheme
2340
SDMA Controller Integration
2341
Dma4_Ocp_Sysconfig
2342
SDMA Interrupts
2343
SDMA Request Mapping
2343
Dma4_Irqenable_Lj
2343
Dma4_Csri
2343
SDMA Controller Top-Level Block Diagram
2346
Dma4_Gcr
2347
Example Showing Double-Index Addressing, Elements, Frames, and Strides
2350
Addressing Mode Example (A)
2350
Addressing Mode Example (B)
2350
Addressing Mode Example (C)
2351
Parameter Values for Addressing Mode Examples (A), (B), and (C)
2351
Equations for Rotation
2351
Example of a 90° Clockwise Image Rotation
2352
Example Parameter Values for a 90° Clockwise Image Rotation
2352
Dma4_Ccri
2354
Buffering Disable
2355
Dma4_Clnk_Ctrli
2357
Logical DMA Channel Events
2358
Dma4_Irqstatus_Lj
2358
Dma4_Cicri
2358
Dma4_Csfii
2358
Dma4_Cdpi
2361
Dma4_Cndpi
2361
Dma4_Csdpi
2362
Type 2 with Source and Destination Address Updates
2363
Type 2 with Source or Destination Address Update
2364
Type 3 with Source and Destination Address Updates
2364
Type 3 with Source or Destination Address Update
2364
Dma4_Cceni
2365
Dma4_Ccfni
2365
Dma4_Ccdni
2365
Dma4_Ceni
2368
Dma4_Cfni
2368
Dma4_Cssai
2368
Dma4_Cdsai
2372
SDMA Instance Summary
2374
SDMA Register Summary
2374
Dma4_Revision
2374
Dma4_Sysstatus
2374
Dma4_Cseii
2374
Dma4_Cdeii
2374
Dma4_Cdfii
2374
Dma4_Csaci
2374
Dma4_Cdaci
2374
Dma4_Colori
2374
Dma4_Caps_0
2378
Register Call Summary for Register DMA4_CAPS_0
2379
Dma4_Caps_2
2379
Register Call Summary for Register DMA4_CAPS_2
2380
Dma4_Caps_3
2380
Register Call Summary for Register DMA4_CAPS_3
2381
Dma4_Caps_4
2382
Register Call Summary for Register DMA4_CAPS_4
2383
Interrupt Controllers Highlight
2405
Interrupts from External Devices
2406
MPU Subsystem INTCPS Integration
2407
MPU Subsystem INTC Clock Rates
2407
Hardware and Software Reset
2408
Interrupt Lines Incoming and Outgoing
2408
Interrupt Mapping to the MPU Subsystem
2408
Top-Level Block Diagram
2412
Intcps_Sir_Irq
2416
Intcps_Control
2416
IRQ/FIQ Processing Sequence
2417
Intcps_Irq_Priority
2418
Intcps_Threshold
2418
Nested IRQ/FIQ Sequence
2420
INTC Instance Summary
2422
MPU INTC Register Summary
2422
Modem INTC Register Summary
2422
SCM Overview
2436
SCM Environment Overview
2437
SCM Interface Signals
2438
SCM I/O Description
2438
SCM Integration
2439
Internal Clock Implementation
2442
SCM Block Diagram
2443
Pad Configuration Register Functionality
2444
Pad Configuration Diagram
2446
Mode Selection
2446
Pull Selection
2447
Core Control Module Pad Configuration Register Fields
2448
Core Control Module D2D Pad Configuration Register Fields
2458
Wkup Control Module Pad Configuration Register Fields
2462
Off Mode Pad Control Overview
2464
Save-And-Restore Mechanism Overview
2465
Wake-Up Event Detection Overview
2466
Functional Block Diagram
2467
PBIAS Cell and Extended-Drain I/O Pin Bit Controls
2467
Power Supplies
2468
Extended-Drain I/O
2470
Functional Block Diagram
2471
Band Gap Voltage and Temperature Sensor Signals Description
2472
Single Conversion Mode (CONTCONV = 0)
2473
Continuous Conversion Mode (CONTCONV = 1)
2473
ADC Code Versus Temperature
2473
Msuspendmux Control Registers
2475
IVA2.2 Boot Registers
2475
Control_Iva2_Bootmod
2475
IVA2.2 Boot Modes
2476
PBIAS Control Register
2476
Temperature Sensor Register
2476
Signal Integrity Parameter Control Registers
2476
Control_Prog_Io2
2476
Control_Prog_Io0
2476
Control_Prog_Io1
2476
DS Parameter Settings
2477
LB Parameter Settings for High-Speed I/O Cells
2477
Recommended SC Vs LB Parameter Settings for TL with Length in the Range 2-20Cm
2477
Recommended SC Vs LB Parameter Settings for Dual TL with Length in the Range 20-40Cm
2477
Group Pullup Strength Setting for SDMMC1 I/Os
2478
Example I2Cx Pullupresx Vs I2C LB Parameter Settings in Different Modes
2478
Internal Pullup Resistor in Fast/Hs Mode
2478
Signal Group Parameter Controls to Different Interface I/O Pads Mapping
2479
Protection Status Registers
2484
Overview of the Debug and Observability Register Functionality
2486
Observability Registers
2486
Internal Signals Multiplexed on OBSMUX0
2488
Internal Signals Multiplexed on OBSMUX1
2489
Internal Signals Multiplexed on OBSMUX2
2489
Internal Signals Multiplexed on OBSMUX3
2490
Internal Signals Multiplexed on OBSMUX4
2491
Internal Signals Multiplexed on OBSMUX5
2492
Internal Signals Multiplexed on OBSMUX6
2492
Internal Signals Multiplexed on OBSMUX7
2494
Internal Signals Multiplexed on OBSMUX8
2495
Internal Signals Multiplexed on OBSMUX9
2496
Internal Signals Multiplexed on OBSMUX10
2497
Internal Signals Multiplexed on OBSMUX11
2498
Internal Signals Multiplexed on OBSMUX12
2499
Internal Signals Multiplexed on OBSMUX13
2499
Internal Signals Multiplexed on OBSMUX14
2500
Internal Signals Multiplexed on OBSMUX15
2501
Internal Signals Multiplexed on OBSMUX16
2502
Internal Signals Multiplexed on OBSMUX17
2503
Internal Signals Multiplexed on WKUPOBSMUX0
2504
Internal Signals Multiplexed on WKUPOBSMUX1
2505
Internal Signals Multiplexed on WKUPOBSMUX2
2506
Internal Signals Multiplexed on WKUPOBSMUX3
2507
Internal Signals Multiplexed on WKUPOBSMUX4
2508
Internal Signals Multiplexed on WKUPOBSMUX5
2509
Internal Signals Multiplexed on WKUPOBSMUX6
2510
Internal Signals Multiplexed on WKUPOBSMUX7
2511
Internal Signals Multiplexed on WKUPOBSMUX8
2512
Internal Signals Multiplexed on WKUPOBSMUX9
2513
Internal Signals Multiplexed on WKUPOBSMUX10
2514
Internal Signals Multiplexed on WKUPOBSMUX11
2515
Internal Signals Multiplexed on WKUPOBSMUX12
2516
Internal Signals Multiplexed on WKUPOBSMUX13
2517
Internal Signals Multiplexed on WKUPOBSMUX14
2518
Internal Signals Multiplexed on WKUPOBSMUX15
2519
Internal Signals Multiplexed on WKUPOBSMUX16
2520
Internal Signals Multiplexed on WKUPOBSMUX17
2521
DPLL with EMI Reduction Feature
2522
DPLL-D Integration
2523
Spreading Generation Block Diagram
2524
Effect of the SSC in Frequency
2525
Effect of the SSC in the Time Domain
2526
Peak Reduction Caused by Spreading
2526
Control Signals
2536
Voltage Configuration
2536
Flow Chart
2537
PBIAS Error Signal Truth Table
2538
VDDS Ramps up before VDD2
2539
Pin Types
2542
I/O Power Optimization Flow Chart
2543
SCM Instance Summary
2545
INTERFACE Register Summary
2545
PADCONFS Register Summary
2545
GENERAL Register Summary
2549
Control_Devconf0
2549
Control_Devconf1
2549
Control_Status
2549
Control_Fuse_Sr
2550
MEM_WKUP Register Summary
2552
PADCONFS_WKUP Register Summary
2552
GENERAL_WKUP Register Summary
2553
Control_Padconf_X
2555
Register Call Summary for Register CONTROL_PADCONF_X
2556
Control_Padconf_Capabilities
2558
Static Device Configuration Registers
2569
Control_Msuspendmux_0
2570
Register Call Summary for Register CONTROL_MSUSPENDMUX_0
2571
Control_Msuspendmux_1
2571
Register Call Summary for Register CONTROL_MSUSPENDMUX_1
2574
Control_Msuspendmux_2
2574
Register Call Summary for Register CONTROL_MSUSPENDMUX_2
2577
Control_Msuspendmux_3
2577
Register Call Summary for Register CONTROL_MSUSPENDMUX_3
2578
Control_Msuspendmux_4
2578
Register Call Summary for Register CONTROL_MSUSPENDMUX_4
2578
Control_Msuspendmux_5
2579
Register Call Summary for Register CONTROL_MSUSPENDMUX_5
2580
Control_Rpub_Key_H_0
2587
Register Call Summary for Register CONTROL_RPUB_KEY_H_0
2587
Control_Rpub_Key_H_1
2588
Register Call Summary for Register CONTROL_RPUB_KEY_H_1
2588
Control_Rpub_Key_H_2
2588
Register Call Summary for Register CONTROL_RPUB_KEY_H_2
2588
Control_Rpub_Key_H_3
2588
Register Call Summary for Register CONTROL_RPUB_KEY_H_3
2588
Control_Rpub_Key_H_4
2589
Register Call Summary for Register CONTROL_RPUB_KEY_H_4
2589
Control_Usb_Conf_0
2589
Register Call Summary for Register CONTROL_USB_CONF_0
2589
Control_Usb_Conf_1
2589
Register Call Summary for Register CONTROL_USB_CONF_1
2590
Control_Fuse_Opp1G2_Vdd1
2590
Register Call Summary for Register CONTROL_FUSE_OPP1G2_VDD1
2590
Control_Fuse_Opp1G_Vdd1
2590
Register Call Summary for Register CONTROL_FUSE_OPP1G_VDD1
2590
Control_Fuse_Opp50_Vdd1
2591
Register Call Summary for Register CONTROL_FUSE_OPP50_VDD1
2591
Control_Fuse_Opp100_Vdd1
2591
Register Call Summary for Register VDD1
2591
Control_Fuse_Opp130_Vdd1
2591
Register Call Summary for Register CONTROL_FUSE_OPP130_VDD1
2592
Control_Fuse_Opp100_2_Vdd2
2592
Register Call Summary for Register CONTROL_FUSE_OPP100_2_VDD2
2592
Control_Fuse_Opp50_Vdd2
2592
Register Call Summary for Register CONTROL_FUSE_OPP50_VDD2
2592
Control_Fuse_Opp100_1_Vdd2
2593
Register Call Summary for Register CONTROL_FUSE_OPP100_1_VDD2
2593
Control_Mem_Rta_Ctrl
2597
Control_Debobs_0
2598
Register Call Summary for Register CONTROL_DEBOBS_0
2598
Control_Debobs_1
2598
Register Call Summary for Register CONTROL_DEBOBS_1
2598
Control_Debobs_2
2599
Register Call Summary for Register CONTROL_DEBOBS_2
2599
Control_Debobs_3
2599
Register Call Summary for Register CONTROL_DEBOBS_3
2599
Control_Debobs_4
2600
Register Call Summary for Register CONTROL_DEBOBS_4
2600
Control_Debobs_5
2600
Register Call Summary for Register CONTROL_DEBOBS_5
2600
Control_Debobs_6
2601
Register Call Summary for Register CONTROL_DEBOBS_6
2601
Control_Debobs_7
2601
Register Call Summary for Register CONTROL_DEBOBS_7
2601
Control_Debobs_8
2602
Register Call Summary for Register CONTROL_DEBOBS_8
2602
Register Call Summary for Register CONTROL_PROG_IO0
2606
Control_Dss_Dpll_Spreading
2609
Control_Core_Dpll_Spreading
2610
Control_Per_Dpll_Spreading
2611
Control_Usbhost_Dpll_Spreading
2611
Sdrcsharing
2612
SDRC Registers
2613
Simplified Block Diagram of the IPC
2646
IPC Integration
2647
Mailbox Block Diagram
2650
Example of Communication
2656
Device MMU Instances
2664
Camera MMU System Integration
2665
IVA2.2 MMU System Integration
2665
Communication Protocol
2666
MMU Address Translation
2668
MMU Usage Examples
2669
MMU Architecture
2670
Translation Process
2671
Translation Hierarchy
2672
First-Level Descriptor Address Calculation
2672
Detailed First-Level Descriptor Address Calculation
2673
Section Translation Summary
2674
Supersection Translation Summary
2675
Two-Level Translation
2675
Small Page Translation Summary
2676
Large Page Translation Summary
2677
TLB Entry Lock Mechanism
2678
TLB Entry Structure
2679
MMU Configuration Strategies
2681
Mmun Translation Table Hierarchy
2683
GP Timers Overview
2703
GP Timers External System Interface
2705
GP Timer Integration
2706
Wake-Up Request Generation
2710
Block Diagram of GPTIMER3 through GPTIMER9 and GPTIMER11
2713
Block Diagram of GPTIMER1, GPTIMER2, and GPTIMER10
2714
Gpti.tcrr Timing Value
2715
Block Diagram of the 1-Ms Tick Module
2716
Capture Wave Example for Gpti.tclr[13] CAPT_MODE
2718
Timing Diagram of PWM with Gpti.tclr[7] SCPWM Bit
2720
Wdts Block Diagram
2746
WDT Integration
2747
WDT General Functional View
2751
HS I C Controllers Overview Block Diagram
2768
Controllers and Typical Connections to I
2770
Controller Interface Signals in I
2770
HS I C Serial Data Transfer
2771
Bit Data Validity Transfer on the I
2771
HS I C Start and Stop Condition Events
2772
HS I C Data Transfer Formats in F/S Mode
2772
HS I C Data Transfers in HS Mode
2773
Arbitration between Master Transmitters
2774
Synchronization of I
2774
Controllers and Typical Connections to SCCB Devices
2775
Controller Interface Signals in SCCB Mode
2776
3-Wire SCCB Transmission Timing Diagram
2777
HS I C SCCB Transmission Data Formats
2777
Typical Connection between Power Chip(S) and for I2C4
2779
Data Transfer Format in F/S Mode for I2C4
2780
Data Transfer Format in HS Mode for I2C4
2780
HS I C Controller Integration Diagram
2782
Wake-Up Generation Flow
2785
HS I C Controllers Functional Block Diagram
2790
HS I C Receive FIFO Interrupt Request Generation
2792
HS I C Transmit FIFO Interrupt Request Generation
2792
HS I C Receive FIFO DMA Request Generation
2793
Transmit FIFO Request Generation (High Threshold)
2794
HS I C Clock Generation
2796
Mode Setup Procedure
2802
Master Transmitter Mode, Polling Method, in F/S and HS Modes
2803
Master Receiver Mode, Polling Method, in F/S and HS Modes
2804
Master Transmitter Mode, Interrupt Method, in F/S and HS Modes
2805
Master Receiver Mode, Interrupt Method, in F/S and HS Modes
2806
Master Transmitter Mode, DMA Method in F/S and HS Modes
2807
Slave Transmitter/Receiver Mode, Polling
2809
Slave Transmitter/Receiver Mode, Interrupt
2810
Setup Procedure (SCCB Mode)
2812
Master Transmitter Mode, Polling (SCCB Mode)
2813
Master Receiver Mode, Polling (SCCB Mode)
2814
Master Transmitter Mode, Interrupt (SCCB Mode)
2815
Master Receiver Mode, Interrupt (SCCB Mode)
2816
HDQ/1-Wire Highlight
2842
HDQ/1-Wire Typical Application System Overview
2843
HDQ Break-Pulse Timing Diagram
2844
HDQ/1-Wire Transmitted Bit Timing
2845
HDQ/1-Wire Communication Sequence
2845
HDQ/1-Wire Integration
2846
HDQ/1-Wire Block Diagram
2848
Protocol Registers Description
2849
HDQ/1-Wire Configuration in HDQ Mode
2858
Software Reset Flowchart
2859
UART Module
2870
UART Mode Bus System Overview
2873
Irda System Overview
2873
CIR System Overview
2874
UART Frame Data Format
2875
Irda SIR Frame Format
2876
Irda SIR Encoding Mechanism
2877
Irda SIR Decoding Mechanism
2878
SIR Free Format Mode
2879
MIR Transmit Frame Format
2879
MIR Baud Rate Adjustment Mechanism
2880
CIR Pulse Modulation
2882
CIR Modulation Duty Cycle
2883
RC-5 Bit Encoding
2884
SIRC Bit Encoding
2884
SIRC Packet Format
2885
SIRC Bit Transmission Example
2885
UART Functional Integration
2886
Uart/Irda/Cir Block Diagram
2890
FIFO Management Registers
2891
Receive FIFO Interrupt Request Generation
2893
Transmit FIFO Interrupt Request Generation
2893
Receive FIFO DMA Request Generation (32 Characters)
2895
Transmit FIFO DMA Request Generation (56 Spaces)
2895
Transmit FIFO DMA Request Generation (8 Spaces)
2896
Transmit FIFO DMA Request Generation (1 Space)
2897
Transmission Process
2897
Reception Process
2898
Baud Rate Generation
2904
Baud Rate Generator
2911
CIR Mode Block Components
2916
Multichannel Modules SPI1, SPI2, SPI3, and SPI4
2977
Typical Application Using the Mcspi
2979
Mcspi Master Mode (Full-Duplex)
2980
Mcspi Master Single Mode (Receive-Only)
2980
Mcspi Slave Mode (Full Duplex)
2981
Mcspi Slave Single Mode (Transmit Only)
2981
Mcspi Interface Signals in Master Mode
2982
Mcspi Interface Signals in Slave Mode
2982
Phase and Polarity Combinations
2984
Full-Duplex Transfer Format with PHA
2985
Extended SPI Transfer with a Start-Bit (SBE = 1)
2986
Mcspi Integration
2987
Mcspi Block Diagram
2991
SPI Full-Duplex Transmission (Example)
2993
Continuous Transfers with Spim_Csx Maintained Active (Single-Data-Pin Interface Mode)
2995
Continuous Transfers with Spim_Csx Maintained Active (Dual-Data-Pin Interface Mode)
2995
Chip-Select SPIEN Timing Controls
2996
Example of Mcspi Slave with One Master and Multiple Slave Devices on Channel
2999
SPI Half-Duplex Transmission (Transmit-Only Slave)
3001
SPI Half-Duplex Transmission (Receive-Only Slave)
3002
Buffer Use in Transmit Direction Only
3002
Buffer Use in Receive Direction Only
3003
Buffer Used for both Transmit/Receive Directions
3003
Buffer Almost Full Level (AFL)
3004
Buffer Almost Empty Level (AEL)
3004
Module Initialization Flow
3012
Common Transfer Sequence: Main Process
3013
Transmit and Receive (Master and Slave)
3015
Transmit-Only with Interrupts (Master and Slave)
3016
Transmit-Only with DMA (Master and Slave)
3017
Receive Only with Interrupt (Master Normal)
3018
Receive-Only with DMA (Master Normal)
3019
Receive-Only with Interrupt (Master Turbo)
3020
Receive Only (Slave)
3022
Two SPI Transfers with PHA = 0 (Flexibility of Mcspi)
3023
Common Transfer Sequence/Main Process
3026
Transmit-Receive with Word Count
3028
Transmit-Receive Without Word Count
3029
Transmit-Only
3030
Receive-Only with Word Count
3031
Receive-Only Without Word Count
3032
Mcbsp Highlight
3056
SIDETONE Core Architecture
3058
Mode Overview of Mcbsp1 Module
3061
Mode Overview of Mcbspi Module
3062
DBB Data Application
3062
Audio Data Application
3063
Voice Data Application
3063
Mcbsp Reception/Transmission Signal Activity
3065
Serial Data Formats
3065
TDM Data Format; Word Width: 32 Bits; Data Length: 24 Bits
3066
I2S Data Format; Word Width: 32 Bits; Data Length: 24 Bits
3067
Left Justified Data Format; Word Width: 32 Bits; Data Length: 24 Bits
3067
Right Justified Data Format; Word Width: 32 Bits; Data Length: 24 Bits
3067
PCM Protocol - Mode 1 Data Format
3068
PCM Protocol - Mode 2 Data Format
3068
Mcbsp1 Integration
3069
Mcbsp2 Integration
3070
Mcbsp3 Integration
3071
Mcbsp4 Integration
3072
Mcbsp5 Integration
3073
Mcbsp1, Mcbsp4 and Mcbsp5 Block Diagrams
3090
Mcbsp2 Block Diagram
3091
Mcbsp3 Block Diagram
3092
Mcbsp Data Transfer Paths
3093
Mcbsp2 Data Transfer Paths
3093
Conceptual Block Diagram for Clock and Frame Generation
3094
Clock Signal Control of Bit Transfer Timing
3095
Mcbsp Operating at Maximum Packet Frequency
3097
Single-Phase Frame for a Mcbsp Data Transfer
3099
Dual-Phase Frame for a Mcbsp Data Transfer
3100
Mcbsp Reception Physical Data Path
3100
Mcbsp Reception Signal Activity
3100
Mcbsp Transmission Physical Data Path
3101
Mcbsp Transmission Signal Activity
3101
Transmit Full Cycle Timing Diagram
3102
Transmit Half Cycle Timing Diagram
3103
Receive Full Cycle Timing Diagram
3103
Receive Half Cycle Timing Diagram
3103
Conceptual Block Diagram of the Sample Rate Generator
3104
CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 0X1)
3108
CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 0X3)
3108
Overrun in the Mcbsp Receiver
3110
Unexpected Frame-Sync Pulse During a Mcbsp Reception
3110
Proper Positioning of Receive Frame-Sync Pulses
3111
Unexpected Frame-Sync Pulse During a Mcbsp Transmission
3112
Proper Positioning of Transmit Frame-Sync Pulses
3113
Mcbsp Data Transfer in 8-Partition Mode
3116
Alternating between Partitions a and B Channels
3117
Activity on Mcbsp Pins When XMCM=0B00
3119
Activity on Mcbsp Pins When XMCM=0B01
3119
Activity on Mcbsp Pins When XMCM=0B10
3119
Activity on Mcbsp Pins When XMCM=0B11
3120
SIDETONE Data Path
3121
Mcbsp to SIDETONE Data Exchange
3122
SIDETONE to Mcbsp Data Exchange
3122
SIDETONE Processed Data Interfaces
3123
Flow Diagram of Mcbsp Initialization Procedure for Master Mode
3126
Flow Diagram of Mcbsp Initialization Procedure for Slave Mode
3127
Flow Diagram for the SRG Registers Programmation
3130
Important Tasks to Configure the Mcbsp Receiver (Part 1)
3134
Important Tasks to Configure the Mcbsp Receiver (Part 2)
3135
Range of Programmable Data Delay
3137
Data Externally Clocked on a Rising Edge and Sampled on a Falling Edge
3140
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
3141
Important Tasks to Configure the Mcbsp Transmitter (Part 1)
3143
Important Tasks to Configure the Mcbsp Transmitter (Part 2)
3144
Range of Programmable Data Delay
3146
Four 8-Bit Data Words Transferred To/From Mcbsp Module
3151
One 32-Bit Data Word Transferred To/From Mcbsp Module
3151
Configuring the Data Stream as a Continuous 32-Bit Word
3152
USB Modules Overview
3210
High-Speed USB Controller Highlight
3211
High-Speed USB Controller Typical Application System
3213
High-Speed USB Controller Functional Interface Signals
3214
High-Speed USB Controller Integration
3215
High-Speed USB Controller
3221
High-Speed USB OTG Controller Endianess
3224
High-Speed USB Host Subsystem Highlight
3234
USB Connection
3237
High-Speed USB Host Controller Connection-With and Without TLL
3238
High-Speed USB Host Controller Typical Application System - ULPI Interfaces
3239
High-Speed USB Host Subsystem Typical Application System - ULPI TLL Interfaces
3240
ULPI Interfaces - 12-Pin/8-Bit Data SDR Version
3241
ULPI TLL Interfaces - 12-Pin/8-Bit Data SDR Version
3242
ULPI TLL Interfaces - 8-Pin/4-Bit Data DDR Version
3242
High-Speed USB Host Subsystem Functional Interface Signals
3243
High-Speed USB Host Subsystem Typical Application System
3246
Serial Interface Sideband Integration - Transceiver Configuration
3250
Serial Interface Sideband Integration - TLL Configuration
3251
High-Speed USB Subsystem Integration
3261
High-Speed USB Host Controller Architecture
3271
USBTLL Channel
3274
Per-Configuration Datapath through USBTLL
3276
Selecting and Configuring High-Speed USB Host Subsystem Connectivity
3281
Memory Stick PRO Host Controller Overview
3362
MMC/SD/SDIO1 and 3 Overview
3364
MMC/SD/SDIO2 Overview
3365
MMC/SD/SDIO Connected to MMC, SD, or SDIO Card Without External Transceiver
3367
MMC/SD/SDIO2 Connected to MMC, SD, SDIO Card with External Transceiver
3368
MMC/Sd/Sdioi Interface Signals
3368
MMC/SD/SDIO2 Interface Signals
3369
Sequential Read Operation (MMC Cards Only)
3370
Sequential Write Operation (MMC Cards Only)
3370
Multiple Block Read Operation
3371
Multiple Block Write Operation with Card Busy Signal
3371
Command Token Format
3372
Response Token Format (R1, R3, R4, R5, R6)
3372
Response Token Format (R2)
3372
Data Token Format for 1-Bit Transfers
3373
Data Token Format for 4-Bit Transfers
3373
Data Token Format for 8-Bit Transfers
3374
MMC/SD/SDIO1 Integration
3375
DMA Receive Mode
3380
DMA Transmit Mode
3381
MMC/SD/SDIO Diagram
3384
Buffer Management for a Write
3387
Buffer Management for a Read
3388
Busy Timout for R1B, R5B Response Type
3390
Busy Timeout after Write CRC Status
3391
Write CRC Status Timeout
3391
Read Data Timeout
3392
Boot Acknowledge Timeout When Using CMD0
3392
Boot Acknowledge Timeout When CMD Line Tied to
3393
Autocommand 12 Timings During Write Transfer
3393
Autocommand 12 Timings During Read Transfer
3394
MMC/SD/SDIO Controller Meta Initialization Steps
3396
MMC/SD/SDIO Controller Software Reset Flow
3397
MMC/SD/SDIO Controller Wake-Up Configuration
3398
MMC/SD/SDIO Controller Bus Configuration
3399
MMC/SD/SDIO Controller Card Identification and Selection - Part
3400
MMC/SD/SDIO Controller Card Identification and Selection - Part
3401
MMC/SD/SDIO Controller Read/Write Transfer Flow in DMA Mode with Interrupt
3402
MMC/SD/SDIO Controller Read/Write Transfer Flow in DMA Mode with Polling
3403
MMC/SD/SDIO Controller Read/Write Transfer Flow Without DMA and with Polling
3404
MMC/SD/SDIO Controller Read/Write in CE-ATA Mode
3405
MMC/SD/SDIO Controller Suspend Flow
3406
MMC/SD/SDIO Controller Resume Flow
3407
MMC/SD/SDIO Controller Command Transfer Flow with Polling
3408
MMC/SD/SDIO Controller Command Transfer Flow with Interrupts
3409
MMC/SD/SDIO Controller Clock Frequency Change Flow
3410
MMC/SD/SDIO Power Switching Procedure
3411
Command Transfer
3414
Data Read Transfer
3414
Data Write Transfer
3414
General-Purpose Interface Overview
3465
General-Purpose Interface Typical Application System Overview
3466
General-Purpose Interface Used as a Keyboard Interface
3467
General-Purpose Interface Integration
3469
General-Purpose Interface Description
3476
Synchronous Path
3476
Asynchronous Path
3477
Interrupt Request Generation
3478
Wake-Up Request Generation
3479
Write @GPIO_CLEARDATAOUT Register Example
3481
Write @Gpio_Setirqenablex Register Example
3482
Initialization Process
3510
Device and TWL5030 Power Connections
3511
Clock and Reset Environment
3513
Clock Interface
3514
ROM Code Architecture
3522
32KB ROM Memory Map
3523
64KB RAM Memory Map of GP Devices
3525
Overall Booting Sequence
3527
Booting Device List Setup
3530
Common Peripheral Booting Protocol
3532
Peripheral Booting Procedure
3534
Customer USB Descriptor Selection
3539
Fast External Boot Procedure
3541
Memory Booting Procedure
3542
Detailed Memory Booting for Non-XIP Booting Devices
3543
NAND Device Detection
3549
NAND ID2 Detection
3550
Bad NAND Invalid Block Detection
3552
ECC Locations in NAND Spare Areas
3553
ECC Locations in 4-KB Page NAND Spare Areas
3554
MLC NAND Data Encoding
3555
Mlc Nand
3556
Onenand/Flex-Onenand Read Sector
3557
MMC/SD Booting
3559
TWL5030 Connectivity Constraints to Support MMC/Sd/Emmc/Esd Booting on SD/MMC Port
3560
TWL5030 Connectivity Constraints to Support Emmc/Esd Booting on SD/MMC Port
3561
MMC/SD Detection Procedure
3562
SD/MMC Booting
3564
MBR Detection Procedure
3566
Get MBR Partition
3567
Image Format
3570
Format
3571
Sdrc_Sysconfig
3572
Gpmc_Sysconfig
3574
Debug and Emulation Hardware in the Device
3586
Icepick Overview
3588
Icepick Overview
3589
TAP State Transitions
3590
Multiple Read in ROUTER Instruction
3595
Multiple Write in ROUTER Instruction
3595
Mixed Read and Write in ROUTER Instruction
3595
SDTI in the Device
3607
SDTI Connected in Four Data Pins Mode
3608
SDTI Connected in Two Data Pins Mode
3608
SDTI Connected in One Data Pin Mode
3608
Dual-Edge Clock Waveform
3609
Single-Edge Clock Waveform
3609
SDTI Integration
3611
SDTI Block Diagram
3612
EPM Overview
3639
EPM Control Access
3643
Omap36Xx in CYN Package Block Diagram
3652
External Clock Interface
3658
Camera Subsystem Block Diagram
3665
Display Subsystem Block Diagram
3667
Devices
3687
Mode 0
3712
Mode 1
3714
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